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Current implementation > supports 256B as default for DMA channel register space. > CPM6 supports the selection of channel register space via VSEC. > The default value for channel register space for CPM6 is 512B. > > Updated the functions and methods to calculate the DMA channel > registers base address as per the selected channel separation > available as part of 'ch_space_sz'. Removed the unused function > __dw_regs() and structs, namely dw_hdma_v0_ch and dw_hdma_v0_regs. > > Signed-off-by: Devendra K Verma > --- Reviewed-by: Frank Li > Changes in v2: > o Replace 'ch_sep_sz' with 'ch_space_sz' as per review > recommendations. > o As patch 1/3 of previous series dropped after review, > this patch becomes 2/2 of the current series. > > Changes in v1: > o Updated the description as per the review comment > o Updated ch_sep_sz for EPC driver. > --- > drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++++ > drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 ++++++++++++-------- > drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 +++++---------- > drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 --------- > drivers/pci/controller/dwc/pcie-designware.c | 1 + > include/linux/dma/edma.h | 1 + > 6 files changed, 26 insertions(+), 30 deletions(-) > > diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c > index 5d7507a64056..81401620988c 100644 > --- a/drivers/dma/dw-edma/dw-edma-pcie.c > +++ b/drivers/dma/dw-edma/dw-edma-pcie.c > @@ -114,6 +114,7 @@ static const struct dw_edma_pcie_data snps_edda_data = { > .irqs = 1, > .wr_ch_cnt = 2, > .rd_ch_cnt = 2, > + .ch_space_sz = 256, > }; > > static const struct dw_edma_pcie_data xilinx_mdb_data = { > @@ -127,6 +128,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = { > .irqs = 1, > .wr_ch_cnt = 8, > .rd_ch_cnt = 8, > + .ch_space_sz = 256, > }; > > static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { > @@ -140,6 +142,7 @@ static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { > .irqs = 1, > .wr_ch_cnt = 8, > .rd_ch_cnt = 8, > + .ch_space_sz = 512, > }; > > static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, > @@ -436,6 +439,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, > chip->nr_irqs = nr_irqs; > chip->ops = &dw_edma_pcie_plat_ops; > chip->cfg_non_ll = non_ll; > + chip->ch_space_sz = vsec_data->ch_space_sz; > > chip->ll_wr_cnt = vsec_data->wr_ch_cnt; > chip->ll_rd_cnt = vsec_data->rd_ch_cnt; > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > index 632abb8b481c..f8b2383b294a 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > @@ -23,18 +23,23 @@ enum dw_hdma_control { > DW_HDMA_V0_LLE = BIT(9), > }; > > -static inline struct dw_hdma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) > -{ > - return dw->chip->reg_base; > -} > - > static inline struct dw_hdma_v0_ch_regs __iomem * > __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) > { > - if (dir == EDMA_DIR_WRITE) > - return &(__dw_regs(dw)->ch[ch].wr); > - else > - return &(__dw_regs(dw)->ch[ch].rd); > + u32 ch_base; > + > + /* > + * For Write, the channel register index starts at > + * wr_base(ch_idx) = (2 * ch_idx) * ch_space_sz > + * > + * For Read channel, > + * rd_base(ch_idx) = (2 * ch_idx + 1) * ch_space_sz > + */ > + ch_base = 2 * ch; > + if (dir == EDMA_DIR_READ) > + ch_base += 1; > + > + return dw->chip->reg_base + (ch_base * dw->chip->ch_space_sz); > } > > #define SET_CH_32(dw, dir, ch, name, value) \ > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c > index dcdc57fe976c..3fa16e045a58 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c > @@ -13,22 +13,17 @@ > #include "dw-hdma-v0-regs.h" > #include "dw-edma-core.h" > > -#define REGS_ADDR(dw, name) \ > - ({ \ > - struct dw_hdma_v0_regs __iomem *__regs = (dw)->chip->reg_base; \ > - \ > - (void __iomem *)&__regs->name; \ > - }) > - > #define REGS_CH_ADDR(dw, name, _dir, _ch) \ > ({ \ > - struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ > + struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ > + off_t __off = (dw)->chip->ch_space_sz; \ > \ > - if (_dir == EDMA_DIR_READ) \ > - __ch_regs = REGS_ADDR(dw, ch[_ch].rd); \ > + if ((_dir) == EDMA_DIR_READ) \ > + __off *= (2 * (_ch) + 1); \ > else \ > - __ch_regs = REGS_ADDR(dw, ch[_ch].wr); \ > + __off *= (2 * (_ch)); \ > \ > + __ch_regs = ((dw)->chip->reg_base + __off); \ > (void __iomem *)&__ch_regs->name; \ > }) > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h > index 7759ba9b4850..2475b8d96133 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h > +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h > @@ -84,16 +84,6 @@ struct dw_hdma_v0_ch_regs { > }; > } msi_abort; > u32 msi_msgdata; /* 0x00a8 */ > - u32 padding_2[21]; /* 0x00ac..0x00fc */ > -} __packed; > - > -struct dw_hdma_v0_ch { > - struct dw_hdma_v0_ch_regs wr; /* 0x0000 */ > - struct dw_hdma_v0_ch_regs rd; /* 0x0100 */ > -} __packed; > - > -struct dw_hdma_v0_regs { > - struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ > } __packed; > > struct dw_hdma_v0_lli { > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index ec4722ed9303..dfb7deaff751 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -1049,6 +1049,7 @@ static void dw_pcie_edma_init_data(struct dw_pcie *pci) > pci->edma.ops = &dw_pcie_edma_ops; > > pci->edma.flags |= DW_EDMA_CHIP_LOCAL; > + pci->edma.ch_space_sz = 256; > } > > static int dw_pcie_edma_find_mf(struct dw_pcie *pci) > diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h > index 1fafd5b0e315..182d4eeae22a 100644 > --- a/include/linux/dma/edma.h > +++ b/include/linux/dma/edma.h > @@ -104,6 +104,7 @@ struct dw_edma_chip { > > struct dw_edma *dw; > bool cfg_non_ll; > + u32 ch_space_sz; > }; > > /* Export to the platform drivers */ > -- > 2.43.0 >