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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-66acae8584bsm7562472d50.10.2026.08.10.14.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 14:58:21 -0700 (PDT) Date: Mon, 10 Aug 2026 17:58:19 -0400 From: Brian Masney To: Stefan =?iso-8859-1?Q?D=F6singer?= Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Vinod Koul , Neil Armstrong , Russell King , Lee Jones , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev Subject: Re: [PATCH v10 08/12] clk: zte: Introduce a driver for zx297520v3 top clocks Message-ID: References: <20260810-zx29clk-v10-0-63846490712c@gmail.com> <20260810-zx29clk-v10-8-63846490712c@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260810-zx29clk-v10-8-63846490712c@gmail.com> User-Agent: Mutt/2.4.0 (2026-06-19) On Mon, Aug 10, 2026 at 12:28:27AM +0300, Stefan Dösinger wrote: > This register space controls core devices: PLLs, the AHB bus, a lot of > timers, the USB controller, the Cortex M0 processor that boots the board > and a few other devices. For some reason the LTE coprocessor is also > partially controlled by it. The main application processor and DDR > memory are not found here though. > > The register to reboot the board is found here, as well as a register to > control whether watchdog expiries cause a board reset. > > Signed-off-by: Stefan Dösinger Reviewed-by: Brian Masney