From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
samuel.holland@sifive.com, dlan@kernel.org,
dfustini@oss.tenstorrent.com, michal.simek@amd.com,
junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com,
akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn,
luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn,
nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com,
greentime.hu@sifive.com, robin.randhawa@sifive.com,
scott@riscstar.com, dave.patel@riscstar.com,
raymond.mao@riscstar.com, anup@brainfault.org,
pawandeep.oza@oss.qualcomm.com
Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties
Date: Tue, 11 Aug 2026 17:31:56 +0800 [thread overview]
Message-ID: <anrsDDkkOKmnkzAa@plin-1878> (raw)
In-Reply-To: <20260730-glossy-pompous-quokka-c05c60@quoll>
Hi Krzysztof,
On Thu, Jul 30, 2026 at 09:30:24AM +0200, Krzysztof Kozlowski wrote:
> On Thu, Jul 30, 2026 at 12:39:07AM +0800, Yu-Chien Peter Lin wrote:
> > + riscv,pmlwidlist:
> > + $ref: /schemas/types.yaml#/definitions/uint64
> > + description:
> > + Optional bitmask of WIDs available for S-mode and U-mode use on this hart; each
> > + set bit N indicates WID N is available. Firmware may read this to select platform
> > + authorized WIDs for lower-privilege modes.
> > # RISC-V has multiple properties for cache op block sizes as the sizes
> > # differ between individual CBO extensions
> > cache-op-block-size: false
> > diff --git a/Documentation/devicetree/bindings/riscv/worlds.yaml b/Documentation/devicetree/bindings/riscv/worlds.yaml
> > new file mode 100644
> > index 000000000000..cc8b3747591e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/worlds.yaml
>
> Please run scripts/checkpatch.pl on the patches and fix reported
> warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
> patches and (probably) fix more warnings. Some warnings can be ignored,
> especially from --strict run, but the code here looks like it needs a
> fix. Feel free to get in touch if the warning is not clear.
The only issue I got is:
WARNING: DT binding documents should be licensed (GPL-2.0-only OR BSD-2-Clause)
#114: FILE: Documentation/devicetree/bindings/riscv/worlds.yaml:1:
+# SPDX-License-Identifier: (GPL-2.0 OR MIT)
Hope I am not missing other warnings or errors.
Thanks,
Peter Lin
next prev parent reply other threads:[~2026-08-11 9:32 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-29 16:39 [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Yu-Chien Peter Lin
2026-08-10 16:25 ` Conor Dooley
2026-08-11 2:23 ` Yu-Chien Peter Lin
2026-08-11 8:24 ` Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-07-29 18:06 ` Rob Herring (Arm)
2026-08-07 7:57 ` Yu-Chien Peter Lin
2026-07-30 7:30 ` Krzysztof Kozlowski
2026-08-11 9:31 ` Yu-Chien Peter Lin [this message]
2026-07-29 16:39 ` [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-07-29 18:07 ` Rob Herring (Arm)
2026-08-11 9:36 ` Yu-Chien Peter Lin
2026-07-30 7:35 ` Krzysztof Kozlowski
2026-07-30 7:37 ` Krzysztof Kozlowski
2026-08-11 9:42 ` Yu-Chien Peter Lin
2026-07-30 17:36 ` Conor Dooley
2026-08-11 9:59 ` Yu-Chien Peter Lin
2026-08-11 9:41 ` Yu-Chien Peter Lin
2026-07-31 1:43 ` [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Nick Kossifidis
2026-08-04 8:25 ` Yu-Chien Peter Lin
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