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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-52e09974dc5sm71521911cf.1.2026.08.25.08.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 08:44:50 -0700 (PDT) Date: Tue, 25 Aug 2026 11:44:49 -0400 From: Brian Masney To: Christian Marangi Cc: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 2/3] clk: en7523: generalize register clocks function Message-ID: References: <20260819221458.30040-1-ansuelsmth@gmail.com> <20260819221458.30040-3-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260819221458.30040-3-ansuelsmth@gmail.com> User-Agent: Mutt/2.4.0 (2026-06-19) Hi Christian, On Thu, Aug 20, 2026 at 12:14:55AM +0200, Christian Marangi wrote: > Airoha AN7583 SoC will use the same logic used by Airoha EN7581 SoC to > register clocks. Generalize it to register clocks defined in soc_data. > > Add the clocks definition in EN7581 SoC to support this new implementation. > > Signed-off-by: Christian Marangi > --- > drivers/clk/clk-en7523.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > index 5c45aacb6409..924e4f3e36b6 100644 > --- a/drivers/clk/clk-en7523.c > +++ b/drivers/clk/clk-en7523.c > @@ -116,6 +116,7 @@ struct en_rst_data { > > struct en_clk_soc_data { > u32 num_clocks; > + const struct en_clk_desc *base_clks; What do you think about adding a num_base_clks member as well to avoid the soc_data->num_clocks - 1 below? Brian > const struct clk_ops pcie_ops; > int (*hw_init)(struct platform_device *pdev, > struct clk_hw_onecell_data *clk_data); > @@ -714,12 +715,15 @@ static int en7523_clk_hw_init(struct platform_device *pdev, > static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, > struct regmap *map, void __iomem *base) > { > + const struct en_clk_soc_data *soc_data; > struct clk_hw *hw; > u32 rate; > int i; > > - for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { > - const struct en_clk_desc *desc = &en7581_base_clks[i]; > + soc_data = device_get_match_data(dev); > + > + for (i = 0; i < soc_data->num_clocks - 1; i++) { > + const struct en_clk_desc *desc = &soc_data->base_clks[i]; > u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; > int err; > > @@ -1014,6 +1018,7 @@ static const struct en_clk_soc_data en7523_data = { > }; > > static const struct en_clk_soc_data en7581_data = { > + .base_clks = en7581_base_clks, > /* We increment num_clocks by 1 to account for additional PCIe clock */ > .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1, > .pcie_ops = { > -- > 2.53.0 >