From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E6B0A44E66D for ; Tue, 25 Aug 2026 13:12:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787663530; cv=none; b=YtuPxy9fylMxspAbdAlU65+wsOJ+ehpUbk9ypJjxP+qJsDa44tQk2eyDNR3DYTD8wjj4Hh3ReJHsASyDjFlkdQedwoQXaOXJuStaNNQVA/V5vdqN56UlZFcknZbIZV0+UP36/Y0EJoGZjVtk1n2umNE8RE2WbQH5S1BphIzOWds= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787663530; c=relaxed/simple; bh=ip74jrEBcTzJPtVOaT/s5xoO1C2OZn6vFIy6/oB81rg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=jvgCO1nVM7XIsvF5n0/ZcI/h/cZceIsk7jtMJx5hxU2VPW5vR50PEHat0E/55tncJvfKBQ8yHZsPaaht2uyUp596J1F8S6qS7sofYY3jY5heLk+RkJ+wQH3slDWisn08SPR0mswUl6bB4oiKSlTugG9MOmXLya+wBZ0c8/c458g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=k7T/fqpB; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="k7T/fqpB" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1B9C71BA8 for ; Tue, 25 Aug 2026 06:11:54 -0700 (PDT) Received: from [192.168.0.1] (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AF3893F66F for ; Tue, 25 Aug 2026 06:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1787663517; bh=ip74jrEBcTzJPtVOaT/s5xoO1C2OZn6vFIy6/oB81rg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=k7T/fqpBxbRlVAwpc6JK0LT9jU+LQuUAA4+uKBnG3sF5jNRr4PkNGdi7k85T6Ms/9 4lNqHscOhgqWABwurTTVbPQR6GOUIi7UeWm66Chm2N+vAAd9If2eJlxnT32sEApLZO KHAvvo2PKzr6qKG3NykE6JDfc0uEK6uWkVxhEzlE= Date: Tue, 25 Aug 2026 14:11:46 +0100 From: Liviu Dudau To: Steven Price Cc: Nicolas Frattaroli , Boris Brezillon , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Grant Likely , Heiko Stuebner , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com Subject: Re: [PATCH v4 2/3] drm/panthor: Revisit reqs_lock handling in flush/reset paths Message-ID: References: <20260812-panthor-cache-flush-fix-v4-0-751e32901898@collabora.com> <20260812-panthor-cache-flush-fix-v4-2-751e32901898@collabora.com> <3ee78a7a-3600-4b44-bf8b-1ff99b693cda@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3ee78a7a-3600-4b44-bf8b-1ff99b693cda@arm.com> On Wed, Aug 19, 2026 at 04:37:27PM +0100, Steven Price wrote: > On 12/08/2026 15:07, Nicolas Frattaroli wrote: > > panthor_gpu_flush_caches() and panthor_gpu_soft_reset() acquire their > > reqs_lock spinlock with the IRQ-disabling variants of the spinlocking > > functions. This isn't necessary, as the lock is never taken from an > > atomic context, as Panthor uses threaded interrupt handlers. The result > > of this overly strict locking is that IRQs may be disabled more > > frequently and for longer than they should be, resulting in increased > > system latency. > > > > Switch the locking to use non-IRQ-disabling scoped_guard statements for > > locking. The wait_event_timeout read of pending_reqs outside of the > > spinlock is fine as wait_event_timeout is a memory barrier according to > > the Linux Memory Model. > > > > Fixes: 5cd894e258c4 ("drm/panthor: Add the GPU logical block") > > Reviewed-by: Boris Brezillon > > Signed-off-by: Nicolas Frattaroli > > Reviewed-by: Steven Price > > Although one minor formatting nit below. > > > --- > > drivers/gpu/drm/panthor/panthor_gpu.c | 72 ++++++++++++++++------------------- > > 1 file changed, 33 insertions(+), 39 deletions(-) > > > > diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c > > index 7088371c6d64..55e33f145b40 100644 > > --- a/drivers/gpu/drm/panthor/panthor_gpu.c > > +++ b/drivers/gpu/drm/panthor/panthor_gpu.c > > @@ -345,41 +345,36 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev, > > u32 l2, u32 lsc, u32 other) > > { > > struct panthor_gpu *gpu = ptdev->gpu; > > - unsigned long flags; > > u64 start = 0; > > int ret = 0; > > > > /* Serialize cache flush operations. */ > > guard(mutex)(&ptdev->gpu->cache_flush_lock); > > > > - spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); > > - > > - if (tracepoint_enabled(gpu_cache_flush)) > > - start = ktime_get_ns(); > > - > > - if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) { > > - ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED; > > - gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); > > - } else { > > - ret = -EIO; > > - } > > - spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); > > - > > - if (ret) { > > - panthor_gpu_emit_flush_caches_tp(ptdev, start, l2, lsc, other, ret); > > - return ret; > > + scoped_guard(spinlock, &ptdev->gpu->reqs_lock) { > > + if (tracepoint_enabled(gpu_cache_flush)) > > + start = ktime_get_ns(); > > + > > + if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) { > > + ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED; > > + gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); > > + } else { > > + panthor_gpu_emit_flush_caches_tp(ptdev, start, l2, lsc, > > + other, -EIO); > > + return -EIO; > > + } > > } > > > > if (!wait_event_timeout(ptdev->gpu->reqs_acked, > > !(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED), > > msecs_to_jiffies(100))) { > > - spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); > > - if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 && > > - !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED)) > > - ret = -ETIMEDOUT; > > - else > > - ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED; > > - spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); > > + scoped_guard(spinlock, &ptdev->gpu->reqs_lock) { > > + if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 && > > + !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED)) > > NIT: This isn't aligned correctly with the if() above any more. I've fixed this locally before pushing it to drm-misc-next. Best regards, Liviu > > To be honest what we really need here is a helper for this sequence as > there's basically the same code again in panthor_gpu_soft_reset() below. > > > + ret = -ETIMEDOUT; > > + else > > + ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED; > > + } > > } > > > > panthor_gpu_emit_flush_caches_tp(ptdev, start, l2, lsc, other, ret); > > @@ -402,27 +397,26 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev) > > { > > struct panthor_gpu *gpu = ptdev->gpu; > > bool timedout = false; > > - unsigned long flags; > > > > - spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); > > - if (!drm_WARN_ON(&ptdev->base, > > - ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) { > > - ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED; > > - gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED); > > - gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET); > > + scoped_guard(spinlock, &ptdev->gpu->reqs_lock) { > > + if (!drm_WARN_ON(&ptdev->base, > > + ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) { > > + ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED; > > + gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED); > > + gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET); > > + } > > } > > - spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); > > > > if (!wait_event_timeout(ptdev->gpu->reqs_acked, > > !(ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED), > > msecs_to_jiffies(100))) { > > - spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); > > - if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 && > > - !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED)) > > - timedout = true; > > - else > > - ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED; > > - spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); > > + scoped_guard(spinlock, &ptdev->gpu->reqs_lock) { > > + if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 && > > + !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED)) > > NIT: Same issue here. > > Thanks, > Steve > > > + timedout = true; > > + else > > + ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED; > > + } > > } > > > > if (timedout) { > > > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯