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Fri, 21 Aug 2026 03:47:13 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-395c42076b6sm2693547a91.0.2026.08.21.03.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 03:47:12 -0700 (PDT) Date: Fri, 21 Aug 2026 16:17:05 +0530 From: Abhinaba Rakshit To: Konrad Dybcio Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev , Kuldeep Singh , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v11 1/6] soc: qcom: ice: Add OPP-based clock scaling support for ICE Message-ID: References: <20260609-enable-ice-clock-scaling-v11-0-1cebc8b3275b@oss.qualcomm.com> <20260609-enable-ice-clock-scaling-v11-1-1cebc8b3275b@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: 9FNyx1sM9kplWbaBvYDay46rS7khlaPj X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfX55v1wNGQaSeE jpKmrwHbpSpEbcOQIWfGTxo47TF4QDl8xhguTOo+aulYVFVTt7kIB+oVlWMf/Y0jgGc0x/2PTnM QheESokvjOslQ7OqvZqVdgySji+aco4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfXwU327Jlvk9HD PltZO9U2QTSBzk0pMan35CWRCQZrO+wUCTP1DMnUnki9yIOundgSxDyd+SEemv6Xpr3JuAD5D6H rqjGR55Xk7xFQmVAPX2J4+ATq0Sr9G2WTp0U9QSzyZFVLz5sggQmFYZAibvGX2nlnSkHLr5Kv1h 5ApvFzk1reN7165kZ9fxfjEQ5zfLLbuGqcONHy97CTE11DCHGhlGAls18L+8AwOkE0Efl7FwR8s hXSkMlpSOxMWcZxMvXjTMD6grykIBNV8Pz0t0/pvhi8c6J0NfDgWoYWoZaLHxZGqLug/to9pDOg ietAYAPUXqN2lPkNEVYDUMnVsXQ+gDf6+qm1nij9Y+QEnFdg+JwGB2i87QoF7geC/AiPOpbkT7t a3M1gaFeqmFA/KaQL6Xn/o/aHSayonUhBwsFjTpXAZWrdPr/mHuk0u+pbQLCUIkRDrThG5HPgEJ a7ViRyOyfr+BwH6lvew== X-Proofpoint-GUID: 9FNyx1sM9kplWbaBvYDay46rS7khlaPj X-Authority-Analysis: v=2.4 cv=UtFT8ewB c=1 sm=1 tr=0 ts=6a882cb2 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=K3LgHJ_EJoQmVUSs8ncA:9 a=CjuIK1q_8ugA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_03,2026-08-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 suspectscore=0 bulkscore=0 adultscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210081 On Mon, Jun 29, 2026 at 01:08:08PM +0200, Konrad Dybcio wrote: > On 6/22/26 9:34 AM, Abhinaba Rakshit wrote: > > On Thu, Jun 18, 2026 at 03:01:54PM +0200, Konrad Dybcio wrote: > >> On 6/8/26 11:47 PM, Abhinaba Rakshit wrote: > >>> Register optional operation-points-v2 table for ICE device > >>> during device probe. Attach the OPP-table with only the ICE > >>> core clock. Since, dtbinding is on a transition phase to include > >>> iface clock and clock-names, attaching the opp-table to core clock > >>> remains optional such that it does not cause probe failures. > >>> > >>> Introduce clock scaling API qcom_ice_scale_clk which scale ICE > >>> core clock based on the target frequency provided and if a valid > >>> OPP-table is registered. Use round_ceil passed to decide on the > >>> rounding of the clock freq against OPP-table. Clock scaling is > >>> disabled when a valid OPP-table is not registered. > >>> > >>> This ensures when an ICE-device specific OPP table is available, > >>> use the PM OPP framework to manage frequency scaling and maintain > >>> proper power-domain constraints. > >>> > >>> Also, ensure to drop the votes in suspend to prevent power/thermal > >>> retention. Subsequently restore the frequency in resume from > >>> core_clk_freq which stores the last ICE core clock operating frequency. > >>> > >>> Reviewed-by: Harshal Dev > >>> Signed-off-by: Abhinaba Rakshit > >>> --- > >> > >> [...] > >> > >>> @@ -335,6 +342,11 @@ int qcom_ice_suspend(struct qcom_ice *ice) > >>> { > >>> clk_disable_unprepare(ice->iface_clk); > >>> clk_disable_unprepare(ice->core_clk); > >>> + > >>> + /* Drop the clock votes while suspend */ > >>> + if (ice->has_opp) > >>> + dev_pm_opp_set_rate(ice->dev, 0); > >> > >> The PM core will quiesce the vote as the device suspends, this is > >> unnecessary. Similarly, the rate restore logic will become unnecessary. > >> Especially since dev_pm_opp_set_rate(0) does not actually do any rate > >> setting. > > > > This section was earlier discussed in the patchset v4: > > https://lore.kernel.org/all/7b219a50-6971-4a0c-a465-418f8abd5556@oss.qualcomm.com/ > > The intention here was to drop the RPMh votes once the device goes to suspend same > > as the storage drivers such as mmc drivers does: > > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/mmc/host/sdhci-msm.c#n2946 > > This was done to leave the hanging votes *on* for unused clocks. > > > > However, I get your point, due to mean to say that once device goes to suspend > > and GDSC power-domain will be turned OFF, it will automatically quiesce the > > performance votes? > > When the device's runtime state goes to 'suspended', all votes are > dropped (which then propagates up the power domain tree, effectively > lowering the vote which passes through the GDSC to the parent CX domain) > > i.e. "yes" > Ack, will drop this in next patchseries. Abhinaba Rakshit