From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A79252EA175; Tue, 17 Jun 2025 16:36:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750178177; cv=none; b=hwDWV5jhVoUNHCm2H7rpH3UAeYNRFfCWvK24xyXyplMHOxwpt/p6wyoiNSLX0FjazPq6tbO3gDQgr0heNSHztZWY4aJ5ywqV1cNl2hVs8OuCUSfOKPZtfBNazsU9hJdyaoRPl7nDRoGUVEHhfJLrn/AKrl5EbHBaML5U5abxnm4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750178177; c=relaxed/simple; bh=bq8mzeX0QkCOdRY4fhxPAU9SH5SZwaXWZhjNFAv43gs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=CJHa10ar41jGHr5ygeACaglOVIPfPQLGijtOviHqHUnKnOJSEWaxODaCVcQNfTSSajS2/n1x/BjF39ShR4HzoOvDI4ec+Jd/jjHposZvEoZ+eSpBVIXAAj1+UNsVV8nQC4cEtcDR85rQoEJod6jpHMYeRZ4G3xJ9aJVyBf6seMc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zp8cBVGB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zp8cBVGB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AF174C4CEE3; Tue, 17 Jun 2025 16:36:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750178177; bh=bq8mzeX0QkCOdRY4fhxPAU9SH5SZwaXWZhjNFAv43gs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Zp8cBVGBL3B7+cVLlo2sXCfehRHKX6KHdfgcdm52sZWDHm3d2bqwLjHjaDxfEaNXm l7jhkEsQVj8Q3KbPueqKqAr6t6RLD5OJsbqJ/3nprw/okGoLjvk0sHm235aySHiYsm aWNWSx+G0UhiZQka+dGBUoZX0ov4lmojIL8eB0VAvxupjPqRM/4tCliFQPDTvsv9GA 776WBqzY8WjltACyLYjmf+uqjy0lxPqaQC0t6h+7HxFp+S4jfKzSsOsX8ck1Ic34iS gz/PZIPYTB76w8IKanxrF07tctZIgmI9lE4KqMUFp8POu+vlzmRPTjE2vRYclJ6t9I sJywAxqR/iwyA== Date: Tue, 17 Jun 2025 22:06:05 +0530 From: Manivannan Sadhasivam To: Ziyue Zhang Cc: lpieralisi@kernel.org, kwilczynski@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_qianyu@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com Subject: Re: [PATCH v5 3/4] arm64: dts: qcom: qcs615: enable pcie Message-ID: References: <20250527072036.3599076-1-quic_ziyuzhan@quicinc.com> <20250527072036.3599076-4-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250527072036.3599076-4-quic_ziyuzhan@quicinc.com> On Tue, May 27, 2025 at 03:20:35PM +0800, Ziyue Zhang wrote: > From: Krishna chaitanya chundru > > Add configurations in devicetree for PCIe0, including registers, clocks, > interrupts and phy setting sequence. > > Add PCIe lane equalization preset properties for 8 GT/s. > > Signed-off-by: Krishna chaitanya chundru > Signed-off-by: Ziyue Zhang > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 146 +++++++++++++++++++++++++++ > 1 file changed, 146 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index bb8b6c3ebd03..0af757c45eb2 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -1012,6 +1012,152 @@ mmss_noc: interconnect@1740000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + pcie: pcie@1c08000 { > + device_type = "pci"; > + compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; > + reg = <0x0 0x01c08000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf1d>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x1000>, > + <0x0 0x40100000 0x0 0x100000>, > + <0x0 0x01c0b000 0x0 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config", > + "mhi"; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, > + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; > + bus-range = <0x00 0xff>; > + > + dma-coherent; > + > + linux,pci-domain = <0>; > + num-lanes = <1>; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "msi0", > + "msi1", > + "msi2", > + "msi3", > + "msi4", > + "msi5", > + "msi6", > + "msi7", > + "global"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, > + <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; > + clock-names = "pipe", > + "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a"; > + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; > + assigned-clock-rates = <19200000>; > + > + interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "pcie-mem", "cpu-pcie"; > + > + iommu-map = <0x0 &apps_smmu 0x400 0x1>, > + <0x100 &apps_smmu 0x401 0x1>; > + > + resets = <&gcc GCC_PCIE_0_BCR>; > + reset-names = "pci"; > + > + power-domains = <&gcc PCIE_0_GDSC>; > + > + phys = <&pcie_phy>; > + phy-names = "pciephy"; > + > + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 > + 0x5555 0x5555 0x5555 0x5555>; > + > + operating-points-v2 = <&pcie_opp_table>; > + > + status = "disabled"; > + Please define the PCIe bridge node also. - Mani -- மணிவண்ணன் சதாசிவம்