Re: [PATCH v2 3/8] drm/msm/a6xx: fix incorrectly set uavflagprd_inv field for A650

Akhil P Oommen
2021-05-31T07:34:43Z

On 5/13/2021 10:43 PM, Jonathan Marek wrote:
> Value was shifted in the wrong direction, resulting in the field always
> being zero, which is incorrect for A650.
>
> Fixes: d0bac4e9cd66 ("drm/msm/a6xx: set ubwc config for A640 and A650")
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 727d111a413f..45a6a0fce7d7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -489,7 +489,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
> gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
> gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
> - uavflagprd_inv >> 4 | lower_bit << 1);
> + uavflagprd_inv << 4 | lower_bit << 1);
> gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
> }
>
>
Reviewed-by: Akhil P Oommen <akhilpo@codeaurora.org>

-Akhil.