From: Baolu Lu <baolu.lu@linux.intel.com>
To: Michael Bommarito <michael.bommarito@gmail.com>,
David Woodhouse <dwmw2@infradead.org>,
Joerg Roedel <joro@8bytes.org>
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry
Date: Mon, 1 Jun 2026 13:35:08 +0800 [thread overview]
Message-ID: <b0278f4d-681c-4731-bc8d-130a56e6d935@linux.intel.com> (raw)
In-Reply-To: <20260528025557.3209367-1-michael.bommarito@gmail.com>
On 5/28/26 10:55, Michael Bommarito wrote:
> device_pasid_table_teardown() zeroes the 128-bit scalable-mode context
> entry with context_clear_entry() while the Present bit is still set. This
> creates a window where the hardware can fetch a torn entry, with some
> fields already zeroed while Present is still set, leading to unpredictable
> behavior or spurious faults. The context-cache invalidation is issued only
> after the entry has been zeroed, and intel_pasid_free_table() then frees
> the PASID directory pages, so the IOMMU can keep walking a stale Present=1
> entry that points at freed memory.
>
> While x86 provides strong write ordering, the compiler may reorder the two
> 64-bit writes to the entry, and the hardware fetch is not guaranteed to be
> atomic with respect to multiple CPU writes.
>
> Commit c1e4f1dccbe9d ("iommu/vt-d: Clear Present bit before tearing down
> context entry") fixed this exact pattern in domain_context_clear_one() and
> the copied-context path, but device_pasid_table_teardown() was not
> converted.
>
> Align it with the "Guidance to Software for Invalidations" in the VT-d
> spec, Section 6.5.3.3, using the same ownership handshake as the sibling
> fix: clear only the Present bit, flush it to the IOMMU, perform the
> context-cache invalidation, and only then zero the rest of the entry.
>
> Fixes: 81e921fd32161 ("iommu/vt-d: Fix NULL domain on device release")
> Signed-off-by: Michael Bommarito<michael.bommarito@gmail.com>
> Assisted-by:Claude:claude-opus-4-7
> ---
> Found by static analysis while auditing the callers of context_clear_entry()
> for the same teardown ordering that c1e4f1dccbe9d addressed. This site is
> reachable only in scalable mode, so it does not manifest on the legacy-mode
> hardware available to me; I could not trigger a runtime fault and the change
> is verified by code inspection only, on the same basis as the sibling fix.
> Compile-tested on x86_64 with CONFIG_INTEL_IOMMU; no new warnings.
>
> drivers/iommu/intel/pasid.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Queued for linux-next. Thank you!
next prev parent reply other threads:[~2026-06-01 5:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-28 2:55 [PATCH] iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry Michael Bommarito
2026-06-01 5:35 ` Baolu Lu [this message]
2026-06-11 11:52 ` Jason Gunthorpe
2026-06-13 1:50 ` Baolu Lu
2026-06-01 5:46 ` Baolu Lu
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