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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-845a3fcc82dsm675711b3a.7.2026.06.23.20.16.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jun 2026 20:16:48 -0700 (PDT) Message-ID: Date: Wed, 24 Jun 2026 11:16:39 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 00/15] drm/msm/dp: Prerequisite cleanup for upcoming MST support To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Abhinav Kumar References: <20260609-dp_mstclean-v7-0-ea04113e8233@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: <20260609-dp_mstclean-v7-0-ea04113e8233@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI0MDAyNCBTYWx0ZWRfX8o7fY8ApK4V2 eTpQdj2ZkcwYWlPnNf63kpwbdB8HSIohOF4z4SgBochVS/XIFRKRtOyd1jK2DzOOSP5frDshTpl EayIraqsWKpDtvwzccSR0+CPPsbNSyunGyw494DXbtg7nCg99FouFy0ZyU0Q7B7zgNNdKD0PYHQ 2QFbmMo7sxAIC0x9Jxs9JbVSIRHTZ0KFoQVUNgTzIvwIrw0RL5a+MfDrWJ2Zn8W6YIn8lHbCsIy 1JdZEg88bb9tMQtlcchDpd0D746jdxetZ21eUbvC5jbTDL9Y9QSrFvjxS5b+I/3CpSMQrdXhHhG SoB03nrPTwyn28OkptKQP/mXnOzltGBTILeelITW2ENGEJt4XiysAvY/A93cbDdODf7W2F2p1WE qkRUU2ImQOfdZRrj7mYNukYAkGyZ27xroiWKpuK+nPR7VdfGpsc8Qzb2y0ciWuj/slu4TgrHDDj AkhJyhrZgN8NBnhargw== X-Proofpoint-GUID: uQ91VjjfBPZMXqp7JvsZKNk0X_qq1-oM X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI0MDAyNCBTYWx0ZWRfX2f45jq97cIy9 BPMA39GCczkG0iQWnJCeLZt6lP7RQ0Rc8WYnTje6lTantvJ/W5y25A/b9Uk0ojpR1gSHheH0NfH CGSPXSt9lBvxKLooiDbhDMH5SUxiTrY= X-Proofpoint-ORIG-GUID: uQ91VjjfBPZMXqp7JvsZKNk0X_qq1-oM X-Authority-Analysis: v=2.4 cv=UphT8ewB c=1 sm=1 tr=0 ts=6a3b4c22 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=vQr1noI8oyt6EgD3lKgA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-24_01,2026-06-23_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606240024 On 6/9/2026 5:46 PM, Yongxing Mou wrote: > This series is the SST-only prerequisite portion of the MSM DP MST > work. It refactors the existing DP code paths so that MST can > plug in cleanly in a follow-up series, without bundling the cleanup > with MST functionality in the same submission. > > SST behaviour is preserved end-to-end; no new functionality is added > here. The intent is to land these refactors first to keep the > follow-up MST series focused, smaller, and easier to review. > > Signed-off-by: Yongxing Mou > --- > Changes in v7: > - patch 7: Use WARN_ON_ONCE() when pixel clock is already on. [Konrad] > - Link to v6: https://lore.kernel.org/r/20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com > > Changes in v6: > - patch 4: fixed the RMW comments. [Dmitry] > - patch 10: do not rename the existing struct. [Dmitry] > - Link to v5: https://lore.kernel.org/r/20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com > > Changes in v5: > - Split out from v4: only the SST prerequisite cleanup (patches 1-15) > is sent here; the MST implementation will follow on top. > - Rebased onto linux-next-20260527; adapted bridge callbacks to the > new drm_atomic_commit* API. > - patch 3: added Suggested-by: Dmitry Baryshkov. > - patch 4: fixed "splite" typo, reworded body, added RMW comment > covering both SST and MST paths. [Dmitry] > - patch 10: drop cached panel from msm_dp_ctrl_private; pass panel > explicitly to all stream-related dp_ctrl APIs. [Dmitry] > - patch 13/14: introduce bridge wrappers and atomic_prepare with > drm_atomic_commit* from the start to preserve bisectability. > - patch 15: fixed pass panel inside the func. [Dmitry] > - Link to v4: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com/ > > --- > Abhinav Kumar (6): > drm/msm/dp: break up dp_display_enable into two parts > drm/msm/dp: re-arrange dp_display_disable() into functional parts > drm/msm/dp: allow dp_ctrl stream APIs to use any panel passed to it > drm/msm/dp: split dp_ctrl_off() into stream and link parts > drm/msm/dp: make bridge helpers use dp_display to allow re-use > drm/msm/dp: separate dp_display_prepare() into its own API > > Yongxing Mou (9): > drm/msm/dp: remove cached drm_edid from panel > drm/msm/dp: drop deprecated .mode_set() and use .atomic_enable > drm/msm/dp: move mode setup into msm_dp_panel_init_panel_info() > drm/msm/dp: split msm_dp_ctrl_config_ctrl() into link parts and stream parts > drm/msm/dp: extract MISC1_MISC0 configuration into a separate function > drm/msm/dp: split link setup from source params > drm/msm/dp: move the pixel clock control to its own API > drm/msm/dp: simplify link and clock disable sequence > drm/msm/dp: pass panel to display enable/disable helpers > > drivers/gpu/drm/msm/dp/dp_ctrl.c | 382 ++++++++++++++++++++---------------- > drivers/gpu/drm/msm/dp/dp_ctrl.h | 30 ++- > drivers/gpu/drm/msm/dp/dp_display.c | 273 +++++++++++++------------- > drivers/gpu/drm/msm/dp/dp_display.h | 8 + > drivers/gpu/drm/msm/dp/dp_drm.c | 43 +++- > drivers/gpu/drm/msm/dp/dp_drm.h | 12 -- > drivers/gpu/drm/msm/dp/dp_panel.c | 75 ++----- > drivers/gpu/drm/msm/dp/dp_panel.h | 17 +- > 8 files changed, 451 insertions(+), 389 deletions(-) > --- > base-commit: e7d700e14934e68f86338c5610cf2ae76798b663 > change-id: 20260528-dp_mstclean-f094cea8ca24 > > Best regards, Hi Dmitry, will this series be merged next cycle?