Re: [PATCH v4 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx

Changhuang Liang
2023-04-12T12:43:48Z

On 2023/4/12 19:34, Krzysztof Kozlowski wrote:
> On 12/04/2023 10:45, Changhuang Liang wrote:
>> StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
>> a M31 IP. Add a binding for it.
>
> So this is D-PHY? Or the other patch is D-PHY? The naming is quite
> confusing and your commit msgs are not helping here.
>
> Also the power domain phandle here adds to the confusion.
>

Yes, this is DPHY, DPHY has rx and tx, and last version we are discussing that
use power domain replace syscon:
https://lore.kernel.org/all/5dc4ddc2-9d15-ebb2-38bc-8a544ca67e0d@starfivetech.com/

>>
>> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
>> ---
>> .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 85 +++++++++++++++++++
>> 1 file changed, 85 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
>>
[...]
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + lane_maps:
>
> Why did this appear? Underscores are not allowed. It looks like you
> re-implement some standard property.
>

Will change to lane-maps.
Yes, according to Vinod advice, lane mapping table use device tree
to parse makes sense.

>> + $ref: /schemas/types.yaml#/definitions/uint8-array
>> + description:
>> + D-PHY rx controller physical lanes and logic lanes mapping table.
>> + items:
>> + - description: logic lane index point to physical lane clock lane 0
>> + - description: logic lane index point to physical lane data lane 0
>> + - description: logic lane index point to physical lane data lane 1
>> + - description: logic lane index point to physical lane data lane 2
>> + - description: logic lane index point to physical lane data lane 3
>> + - description: logic lane index point to physical lane clock lane 1
>> +
>
>
> Best regards,
> Krzysztof
>