Re: [PATCH v3 1/5] drm/msm/a8xx: Fix RSCC offset

[Akhil P Oommen <akhilpo@oss.qualcomm.com>]

On 5/12/2026 1:36 AM, Akhil P Oommen wrote:
> In A8xx, the RSCC block is part of GPU's register space. Update the
> virtual base address of rscc to point to the correct address.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

Missed the Fixes tag:

Fixes: 50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x GMU")

-Akhil

> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 1b44b9e21ad8..cab4c46c6cf2 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -2357,7 +2357,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
>  			goto err_mmio;
>  		}
>  	} else if (adreno_is_a8xx(adreno_gpu)) {
> -		gmu->rscc = gmu->mmio + 0x19000;
> +		/*
> +		 * On a8xx , RSCC lives at GPU base + 0x50000, which falls
> +		 * inside the GPU's kgsl_3d0_reg_memory range rather than the
> +		 * GMU's.
> +		 */
> +		gmu->rscc = gpu->mmio + 0x50000;
>  	} else {
>  		gmu->rscc = gmu->mmio + 0x23000;
>  	}
>