From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 14B073A4F4A for ; Fri, 10 Jul 2026 06:24:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783664672; cv=none; b=fwgGYdNk47qdwyks/EG/EXm96hP6Do4mM4LxFKmhsCl+9h6QD+hKjk7UQd7wPwQuGThQsCeEc2K+9MFAiq4yweJjlXi/hLZ5gOw22Q3z5kxL6j4LB553whslpEinlyZZuq5Zf8s9dSJ6x7ikHmJw/gmKIMZAQ8Jqk3dnrcN0ssw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783664672; c=relaxed/simple; bh=4g/2ofQNJW3nisoY9ATp9Y+hKY3z5NvZnpw6COVHkl4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=FvVoVN4LU0ymXoDaiOLylRQcc/Nnqgoq3gsGxmixjAKf9Y9txt2UzY75PoL4lw4V5wkYKhq9QNwnp9x5bV5pj6m6QMxwEUNoFu3ekboRDAFq7+qgSt9QoO8L3FRHWQyaksZYWF+wIdMvfrZe1O9grCx5WruZrD40nqxGpxqK7mY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=MIHz4ZYt; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="MIHz4ZYt" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F32621684; Thu, 9 Jul 2026 23:24:25 -0700 (PDT) Received: from [10.174.42.251] (unknown [10.174.42.251]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 790453F66F; Thu, 9 Jul 2026 23:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783664670; bh=4g/2ofQNJW3nisoY9ATp9Y+hKY3z5NvZnpw6COVHkl4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=MIHz4ZYtQjRT0S2VjBOcVjsH8pK0JvjY4+hj0w+KPTIEavzgyJ2pd1QRs9meIP7pz 8gHMGGQqraK/YfVihyw+0okzs/RhHWdAsUnhGw+69XsiphjmiROpqG7tMVrHl7rVDl d1ORqkty+KW2ShYAMj2JErgl5mZ8XA/1KWfSGR2s= Message-ID: Date: Fri, 10 Jul 2026 11:54:24 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list To: Suzuki K Poulose , Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260708144331.679816-1-linu.cherian@arm.com> <20260708144331.679816-4-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 08/07/26 8:23 PM, Suzuki K Poulose wrote: > On 08/07/2026 15:43, Linu Cherian wrote: >> Add below cpus to the midr list, which supports >> BBML2_NOABORT. >> >> Cortex A520(AE) >> Cortex A715 >> Cortex A720(AE) >> Cortex A725 >> Neoverse N3 >> C1-Nano >> C1-Pro >> C1-Ultra >> C1-Premium >> >> C1-Ultra and C1-Premium both suffer from erratum 3683289, >> where Break-Before-Make must be followed to avoid a livelock. >> For both CPUs, the erratum is fixed from r1p1. >> Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. > > Please could you also update the list of errata here : > > Documentation/arch/arm64/silicon-errata.rst Agreed. There are existing errata entries for C1-Ultra and C1-Premimum although this errata will not have any corresponding ARM64_ERRATUM_ associated for now. > >> >> The relevant SDENs are: >> * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ >> * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ >> >> Signed-off-by: Linu Cherian >> --- >>   arch/arm64/kernel/cpufeature.c | 9 +++++++++ >>   1 file changed, 9 insertions(+) >> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 9a22df0c5120..adcabea80fcb 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void) >>           MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), >>           MIDR_ALL_VERSIONS(MIDR_AMPERE1), >>           MIDR_ALL_VERSIONS(MIDR_AMPERE1A), >> +        MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), >> +        MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), >> +        MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), >> +        MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), >> +        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), >> +        MIDR_ALL_VERSIONS(MIDR_C1_NANO), >> +        MIDR_ALL_VERSIONS(MIDR_C1_PRO), > > And mention it here, so that it is evident from the code alone ? > >> +        MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), >> +        MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), > > > Suzuki > > >>           {} >>       }; >>   >