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2025 11:17:09 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] i2c: tegra: Add logic to support different register offsets To: Jon Hunter , akhilrajeev@nvidia.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, ldewangan@nvidia.com, digetx@gmail.com, smangipudi@nvidia.com, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251001153648.667036-1-kkartik@nvidia.com> <20251001153648.667036-2-kkartik@nvidia.com> Content-Language: en-US From: Kartik Rajput In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: PN4P287CA0110.INDP287.PROD.OUTLOOK.COM (2603:1096:c01:2ad::11) To MN0PR12MB5716.namprd12.prod.outlook.com (2603:10b6:208:373::14) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6acc3370-5165-403e-b988-08de15e5846d X-MS-Exchange-CrossTenant-AuthSource: MN0PR12MB5716.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2025 05:47:45.0037 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LyK9QWIweRkMmvtx7bje5fU/4s5yT3H+Gu0HzWlJekQZL2LxnHeNJyn/f8tB4zIbaQI/M3nx3bBUKlNfeYb9jw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9228 On 24/10/25 20:43, Jon Hunter wrote: > > On 01/10/2025 16:36, Kartik Rajput wrote: >> Tegra410 use different offsets for existing I2C registers, update >> the logic to use appropriate offsets per SoC. >> >> Signed-off-by: Kartik Rajput >> --- >>   drivers/i2c/busses/i2c-tegra.c | 499 ++++++++++++++++++++++----------- >>   1 file changed, 334 insertions(+), 165 deletions(-) >> >> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c >> index 038809264526..1e26d67cbd30 100644 >> --- a/drivers/i2c/busses/i2c-tegra.c >> +++ b/drivers/i2c/busses/i2c-tegra.c > > ... > >> +static const struct tegra_i2c_regs tegra20_i2c_regs_vi = { >> +    .cnfg = 0x0c00 + (0x000 << 2), >> +    .status = 0x0c00 + (0x01c << 2), >> +    .sl_cnfg = 0x0c00 + (0x020 << 2), >> +    .sl_addr1 = 0x0c00 + (0x02c << 2), >> +    .sl_addr2 = 0x0c00 + (0x030 << 2), >> +    .tlow_sext = 0x0c00 + (0x034 << 2), >> +    .tx_fifo = 0x0c00 + (0x050 << 2), >> +    .rx_fifo = 0x0c00 + (0x054 << 2), >> +    .packet_transfer_status = 0x0c00 + (0x058 << 2), >> +    .fifo_control = 0x0c00 + (0x05c << 2), >> +    .fifo_status = 0x0c00 + (0x060 << 2), >> +    .int_mask = 0x0c00 + (0x064 << 2), >> +    .int_status = 0x0c00 + (0x068 << 2), >> +    .clk_divisor = 0x0c00 + (0x06c << 2), >> +    .bus_clear_cnfg = 0x0c00 + (0x084 << 2), >> +    .bus_clear_status = 0x0c00 + (0x088 << 2), >> +    .config_load = 0x0c00 + (0x08c << 2), >> +    .clken_override = 0x0c00 + (0x090 << 2), >> +    .interface_timing_0 = 0x0c00 + (0x094 << 2), >> +    .interface_timing_1 = 0x0c00 + (0x098 << 2), >> +    .hs_interface_timing_0 = 0x0c00 + (0x09c << 2), >> +    .hs_interface_timing_1 = 0x0c00 + (0x0a0 << 2), >> +    .master_reset_cntrl = 0x0c00 + (0x0a8 << 2), >> +    .mst_fifo_control = 0x0c00 + (0x0b4 << 2), >> +    .mst_fifo_status = 0x0c00 + (0x0b8 << 2), >> +    .sw_mutex = 0x0c00 + (0x0ec << 2), > > Why do we define all the above with '<< 2'? Seems odd. > > Jon > Ack. I will update this with the calculated values. Thanks, Kartik