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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney+clk@redhat.com>,
	Jerome Brunet <jbrunet+clk@baylibre.com>,
	Ulf Hansson <ulfh@kernel.org>
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-pm@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 02/10] dt-bindings: power: Add r8a774a3 SYSC power domain definitions
Date: Sat, 22 Aug 2026 09:29:47 +0200	[thread overview]
Message-ID: <b2f486b8-a391-41bc-8a7f-dc81c6752205@kernel.org> (raw)
In-Reply-To: <20260821150408.73829-3-ayman.chaudhry.kc@renesas.com>

On 21/08/2026 17:03, Ayman Chaudhry wrote:
> This patch adds power domain indices for the Renesas RZ/G2M v3.0


Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94

> (a.k.a. R8A774A3) SoC.
> 
> Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
> ---
>  include/dt-bindings/power/r8a774a3-sysc.h | 30 +++++++++++++++++++++++

Filename must match compatible.


>  1 file changed, 30 insertions(+)
>  create mode 100644 include/dt-bindings/power/r8a774a3-sysc.h
> 
> diff --git a/include/dt-bindings/power/r8a774a3-sysc.h b/include/dt-bindings/power/r8a774a3-sysc.h
> new file mode 100644
> index 000000000000..5694a422b771
> --- /dev/null
> +++ b/include/dt-bindings/power/r8a774a3-sysc.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_POWER_R8A774A3_SYSC_H__
> +#define __DT_BINDINGS_POWER_R8A774A3_SYSC_H__
> +
> +/*
> + * These power domain indices match the numbers of the interrupt bits

No, that's not a binding then.

Also, why is this sent separately from the binding?

> + * representing the power areas in the various Interrupt Registers
> + * (e.g. SYSCISR, Interrupt Status Register)
> + */
> +
> +#define R8A774A3_PD_CA57_CPU0		 0
> +#define R8A774A3_PD_CA57_CPU1		 1
> +#define R8A774A3_PD_CA53_CPU0		 5

No, value is 2. Or not a binding.

Best regards,
Krzysztof

  reply	other threads:[~2026-08-22  7:29 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 01/10] soc: renesas: Identify RZ/G2M v3.0 SoC Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 02/10] dt-bindings: power: Add r8a774a3 SYSC power domain definitions Ayman Chaudhry
2026-08-22  7:29   ` Krzysztof Kozlowski [this message]
2026-08-21 15:03 ` [PATCH 03/10] pmdomain: renesas: rcar-sys: Add r8a774a3 support Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 04/10] soc: renesas: Enable SYSC driver for r8a774a3 Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 05/10] soc: renesas: rcar-rst: Add support for RZ/G2M v3.0 Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 06/10] dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions Ayman Chaudhry
2026-08-22  7:31   ` Krzysztof Kozlowski
2026-08-21 15:03 ` [PATCH 07/10] clk: renesas: Add support for RZ/G2M v3.0 Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 08/10] arm64: dts: renesas: Add initial SoC DTSI " Ayman Chaudhry
2026-08-22  7:38   ` Krzysztof Kozlowski
2026-08-21 15:03 ` [PATCH 09/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support Ayman Chaudhry
2026-08-22  7:34   ` Krzysztof Kozlowski
2026-08-21 15:03 ` [PATCH 10/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC sub " Ayman Chaudhry

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