Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

Thomas Gleixner
2018-10-03T06:10:42Z

On Tue, 2 Oct 2018, kan.liang@linux.intel.com wrote:
> +static bool intel_atom_v4_counter_freezing_broken(int cpu)
> {
> u32 rev = UINT_MAX; /* default to broken for unknown stepping */
>
> - switch (cpu_data(cpu).x86_stepping) {
> - case 1:
> - rev = 0x28;
> + switch (cpu_data(cpu).x86_model) {
> + case INTEL_FAM6_ATOM_GOLDMONT:
> + switch (cpu_data(cpu).x86_stepping) {
> + case 2:
> + rev = 0xe;
> + break;
> + case 9:
> + rev = 0x2e;
> + break;
> + case 10:
> + rev = 0x8;
> + break;
> + }
> break;
> - case 8:
> - rev = 0x6;
> +
> + case INTEL_FAM6_ATOM_GOLDMONT_X:
> + switch (cpu_data(cpu).x86_stepping) {
> + case 1:
> + rev = 0x1a;
> + break;
> + }
> break;
> +
> + case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
> + switch (cpu_data(cpu).x86_stepping) {
> + case 1:
> + rev = 0x28;
> + break;
> + case 8:
> + rev = 0x6;
> + break;
> + }
> }
>
> return (cpu_data(cpu).microcode < rev);

There is another variant of model/stepping micro code verification code in
intel_snb_pebs_broken(). Can we please make this table based and use a
common function? That's certainly not the last quirk we're going to have.

We already have a table based variant of ucode checking in
bad_spectre_microcode(). It's trivial enough to generalize that.

Thanks,

tglx