Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

Liang, Kan
2018-10-03T14:15:40Z

On 10/3/2018 9:55 AM, Thomas Gleixner wrote:
> On Wed, 3 Oct 2018, Liang, Kan wrote:
>> On 10/3/2018 2:10 AM, Thomas Gleixner wrote:
>>> There is another variant of model/stepping micro code verification code in
>>> intel_snb_pebs_broken(). Can we please make this table based and use a
>>> common function? That's certainly not the last quirk we're going to have.
>>>
>>> We already have a table based variant of ucode checking in
>>> bad_spectre_microcode(). It's trivial enough to generalize that.
>>>
>>
>> Sure, I will generalize the bad_spectre_microcode(), rename it to
>> is_bad_intel_microcode(), and move it to
>> arch\x86\kernel\cpu\microcode\intel.c.
>
> I suggest: is_bad_microcode() and have it in cpu/microcode/core.c unless
> you are claiming that bad microcode() is an intel only feature.
>

Yes, other platforms also have microcode issues.
To make it more generic, I think we also need to extend the struct
sku_microcode to check vendor and family.
The "model" in struct x86_cpu_id is u16. I will also change "model" and
"stepping" to u16.

struct sku_microcode {
u16 vendor;
u16 family;
u16 model;
u16 stepping;
u32 microcode;
};

Thanks,
Kan