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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af635aa42cfsm737413066b.103.2025.07.30.05.49.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Jul 2025 05:50:01 -0700 (PDT) Message-ID: Date: Wed, 30 Jul 2025 14:49:58 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq To: Varadarajan Narayanan , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, ilia.lin@kernel.org, djakov@kernel.org, quic_srichara@quicinc.com, quic_mdalam@quicinc.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20250730081316.547796-1-quic_varada@quicinc.com> <20250730081316.547796-5-quic_varada@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250730081316.547796-5-quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMwMDA5MSBTYWx0ZWRfX8jXu2Bp+vf4f nrMJNacVVA2EH9SSPAZKVU56F+KkVeS/Lc2AYTxd5ngcmkSAd0XTGnzhVJ1SRGJ1G2IkbdrQIqZ F9Oa7ZN+DQK9U+pa6qDtbLTb2VNN80pdYyxJ//IXVRPQ6p+u0ydftN9XJI4t/YTmmN4gAUGyGuu tDPtaEd2CpZgqkJLI5G5bKMvnnmOEChYYukXBhdAXVSkx/MdoYhWIk+/avHRQWmQbmoUy+OD5K+ 3hAgNxzcM3/FuxnXjsl8Ngn8ppiuhvg28ozsczmjw485efJEIfW+CHC54JlU+k4DsVc8ztrtRB5 Fhs5QttnSF6oe2o5SzReqSoyXI4NWyMth4WYppjUPEeRRVQpvk09ejNk4Rge1nXm2r5XPJ5A7b+ 3GjEB2hbzCvPdnvEoNqTDH34itFFU7XyjnSaji5w+m/cAkcH4iLpzgL0VnyYp2vZya7xfe7i X-Authority-Analysis: v=2.4 cv=TqLmhCXh c=1 sm=1 tr=0 ts=688a14fc cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=Ba9YZRSbcvaFTVxKLYEA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 9GhylUrvZIGpkbj4thk1nupQiAR_0nwL X-Proofpoint-GUID: 9GhylUrvZIGpkbj4thk1nupQiAR_0nwL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-30_04,2025-07-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxlogscore=855 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507300091 On 7/30/25 10:13 AM, Varadarajan Narayanan wrote: > From: Sricharan Ramabadhran > > Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for > CPU clock scaling. > > Signed-off-by: Sricharan Ramabadhran > [ Added interconnect related entries, fix dt-bindings errors ] > Signed-off-by: Varadarajan Narayanan > --- [...] > + cpu_opp_table: opp-table-cpu { > + compatible = "operating-points-v2-kryo-cpu"; > + opp-shared; > + nvmem-cells = <&cpu_speed_bin>; > + > + opp-1416000000 { These rates seem quite high, are there no lower fstates for idling? > + opp-hz = /bits/ 64 <1416000000>; > + opp-microvolt = <1>; > + opp-supported-hw = <0x3>; > + clock-latency-ns = <200000>; > + opp-peak-kBps = <984000>; > + }; > + > + opp-1800000000 { > + opp-hz = /bits/ 64 <1800000000>; > + opp-microvolt = <2>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + opp-peak-kBps = <1272000>; > + }; > + }; > + > memory@80000000 { > device_type = "memory"; > /* We expect the bootloader to fill in the size */ > @@ -388,6 +428,18 @@ system-cache-controller@800000 { > interrupts = ; > }; > > + qfprom@a6000 { > + compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; > + reg = <0x0 0x000a6000 0x0 0x1000>; The block is a bit bigger On IPQ platforms, can the OS blow fuses directly without TZ interference? > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpu_speed_bin: cpu-speed-bin@234 { > + reg = <0x234 0x1>; > + bits = <0 8>; > + }; > + }; > + > tlmm: pinctrl@1000000 { > compatible = "qcom,ipq5424-tlmm"; > reg = <0 0x01000000 0 0x300000>; > @@ -730,6 +782,15 @@ frame@f42d000 { > }; > }; > > + apss_clk: clock@fa80000 { > + compatible = "qcom,ipq5424-apss-clk"; > + reg = <0x0 0x0fa80000 0x0 0x20000>; Let's make it 0x30_000 to reserve the actual carved out reg space > + clocks = <&xo_board>, <&gcc GPLL0>; > + clock-names = "xo", "clk_ref"; 1 per line would be perfect Konrad