[PATCH v6 0/7] VESA DisplayID spec allows the device to force its DSC bits per pixel value.

[PATCH v6 0/7] VESA DisplayID spec allows the device to force its DSC bits per pixel value.

[Yaroslav Bolyukin]

For example, the HTC Vive Pro 2 VR headset uses this value in
high-resolution modes (3680x1836@90-120, 4896x2448@90-120), and when the
kernel doesn't respect this parameter, garbage is displayed on the HMD
instead.

Me and other users have successfully tested the old (v3) version of this
patch (which was applying DSC BPP value unconditionally, thus incorrect:
https://lkml.org/lkml/2023/2/26/116) on Vive Pro 2 and
Bigscreen Beyond VR headsets, and have been using it daily, it is known
to work and doesn't seem to break anything else since 2022.

Previously, I didn't have enough dedication to get it merged, I hope
this time I will manage to get it to v6.19 :D

Regarding driver support - I have looked at amdgpu and Nvidia's
open-gpu-kernel-modules, and both seem to have some indication for this
value; however, in Linux, it is unused in both.

First patch implements parsing of DSC BPP values and display mode VII
timings flag which mandates that the DSC BPP value should actually be
used for this display mode.

The second patch implements handling of this value for AMDGPU driver.

The only thing that I don't like in the current implementation, is how
the value of `dsc_passthrough_timings_support` flag is propagated from
the connector display modes to the mode created in `DRM_IOCTL_MODE_SETCRTC`
handler (which is used for VR display initialization in Monado and
StreamVR), it feels like this flag should be initialized by the kernel
itself, but as far as I can see there is no correct way to do this, as
the timing constraints calculation belongs to the individual drivers.

Another problem with how this flag is set, is that there is no hard
connection between modes creaded in `SETCRTC` and the modes actually
defined by connector, so the current implementation searches for the
resolution and refresh rate that match exactly declared to obtain
this flag value. This might not be correct, as device might not support
the other mode at all, but the situation won't be any worse for the
existing devices, as the currently they don't work at all, and there
is no other known devices on the market to check their assumption in
regard to this part of specs, and the spec does not describe how that
should work.

Both of those downsides are due to the fact my understanding of DRM
subsystem is not that high. If another implementation would be proposed
by AMDGPU maintainers - I will gladly implement it here.

v5->v6:
 * amdgpu: only apply dsc bpp to modes that match exactly the declared
   modes with this flag set.
v4->v5:
 * The patch was split into multiple
 * Disabled MSO parsing for eDP displays
 * Disabled MSO logs if not used
 * Minor codestyle changes: lines moved around, naming, passing of
   function arguments
v3->v4:
 * This patch now parses timings support flag on type VII block, instead
   of applying it unconditionally. Previously I didn't understand the
   spec properly.
 * Now it also is not being applied for non-supported and/or non-VII
   blocks in amdgpu driver.

Regards,

Lach

Yaroslav Bolyukin (7):
  drm/edid: rename VESA block parsing functions to more generic name
  drm/edid: prepare for VESA vendor-specific data block extension
  drm/edid: MSO should only be used for non-eDP displays
  drm/edid: parse DSC DPP passthru support flag for mode VII timings
  drm/edid: for consistency, use mask everywhere for block rev parsing
  drm/edid: parse DRM VESA dsc bpp target
  drm/amd: use fixed dsc bits-per-pixel from edid

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  16 +++
 drivers/gpu/drm/drm_displayid_internal.h      |  11 ++
 drivers/gpu/drm/drm_edid.c                    | 101 +++++++++++-------
 include/drm/drm_connector.h                   |   6 ++
 include/drm/drm_modes.h                       |  10 ++
 5 files changed, 107 insertions(+), 37 deletions(-)

-- 
2.51.2

[PATCH v6 1/7] drm/edid: rename VESA block parsing functions to more generic name

[Yaroslav Bolyukin]

Those functions would also parse DSC Bits Per Pixel value in the future
commits.

Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 drivers/gpu/drm/drm_edid.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 26bb7710a462..64f7a94dd9e4 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6527,8 +6527,8 @@ static void drm_get_monitor_range(struct drm_connector *connector,
 		    info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
 }
 
-static void drm_parse_vesa_mso_data(struct drm_connector *connector,
-				    const struct displayid_block *block)
+static void drm_parse_vesa_specific_block(struct drm_connector *connector,
+					  const struct displayid_block *block)
 {
 	struct displayid_vesa_vendor_specific_block *vesa =
 		(struct displayid_vesa_vendor_specific_block *)block;
@@ -6587,8 +6587,8 @@ static void drm_parse_vesa_mso_data(struct drm_connector *connector,
 		    info->mso_stream_count, info->mso_pixel_overlap);
 }
 
-static void drm_update_mso(struct drm_connector *connector,
-			   const struct drm_edid *drm_edid)
+static void drm_update_vesa_specific_block(struct drm_connector *connector,
+					   const struct drm_edid *drm_edid)
 {
 	const struct displayid_block *block;
 	struct displayid_iter iter;
@@ -6596,7 +6596,7 @@ static void drm_update_mso(struct drm_connector *connector,
 	displayid_iter_edid_begin(drm_edid, &iter);
 	displayid_iter_for_each(block, &iter) {
 		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
-			drm_parse_vesa_mso_data(connector, block);
+			drm_parse_vesa_specific_block(connector, block);
 	}
 	displayid_iter_end(&iter);
 }
@@ -6756,7 +6756,7 @@ static void update_display_info(struct drm_connector *connector,
 	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
 		info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
 
-	drm_update_mso(connector, drm_edid);
+	drm_update_vesa_specific_block(connector, drm_edid);
 
 out:
 	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_NON_DESKTOP)) {
-- 
2.51.2

[PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Yaroslav Bolyukin]

Current VESA vendor-specific block parsing expects real block size to be
the same as the defined struct size, use real offsets in conditionals
instead to add struct fields in future commits.

Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 64f7a94dd9e4..a52fd6de9327 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
 	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
 		return;
 
-	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
+	if (block->num_bytes < 5) {
 		drm_dbg_kms(connector->dev,
 			    "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
 			    connector->base.id, connector->name);
@@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
 		break;
 	}
 
-	if (!info->mso_stream_count) {
-		info->mso_pixel_overlap = 0;
-		return;
-	}
-
-	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
-	if (info->mso_pixel_overlap > 8) {
+	if (info->mso_stream_count) {
+		info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
+		if (info->mso_pixel_overlap > 8) {
+			drm_dbg_kms(connector->dev,
+				    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
+				    connector->base.id, connector->name,
+				    info->mso_pixel_overlap);
+			info->mso_pixel_overlap = 8;
+		}
 		drm_dbg_kms(connector->dev,
-			    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
+			    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
 			    connector->base.id, connector->name,
-			    info->mso_pixel_overlap);
-		info->mso_pixel_overlap = 8;
+			    info->mso_stream_count, info->mso_pixel_overlap);
 	}
-
-	drm_dbg_kms(connector->dev,
-		    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
-		    connector->base.id, connector->name,
-		    info->mso_stream_count, info->mso_pixel_overlap);
 }
 
 static void drm_update_vesa_specific_block(struct drm_connector *connector,
-- 
2.51.2

[PATCH v6 3/7] drm/edid: MSO should only be used for non-eDP displays

[Yaroslav Bolyukin]

As per DisplayID v2.1a spec:
If Offset 06h[2:0] is programmed to 001b (External DisplayPort), this
field shall be cleared to 00b (Not supported).

Link: https://lore.kernel.org/lkml/3abc1087618c822e5676e67a3ec2e64e506dc5ec@intel.com/
Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 drivers/gpu/drm/drm_displayid_internal.h |  4 +++
 drivers/gpu/drm/drm_edid.c               | 36 +++++++++++++++---------
 2 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
index 5b1b32f73516..72f107ae832f 100644
--- a/drivers/gpu/drm/drm_displayid_internal.h
+++ b/drivers/gpu/drm/drm_displayid_internal.h
@@ -142,9 +142,13 @@ struct displayid_formula_timing_block {
 	struct displayid_formula_timings_9 timings[];
 } __packed;
 
+#define DISPLAYID_VESA_DP_TYPE		GENMASK(2, 0)
 #define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
 #define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
 
+#define DISPLAYID_VESA_DP_TYPE_EDP	0
+#define DISPLAYID_VESA_DP_TYPE_DP	1
+
 struct displayid_vesa_vendor_specific_block {
 	struct displayid_block base;
 	u8 oui[3];
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a52fd6de9327..348aa31aea1b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6533,6 +6533,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
 	struct displayid_vesa_vendor_specific_block *vesa =
 		(struct displayid_vesa_vendor_specific_block *)block;
 	struct drm_display_info *info = &connector->display_info;
+	int dp_type;
 
 	if (block->num_bytes < 3) {
 		drm_dbg_kms(connector->dev,
@@ -6551,20 +6552,29 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
 		return;
 	}
 
-	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
-	default:
-		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
+	dp_type = FIELD_GET(DISPLAYID_VESA_DP_TYPE, vesa->data_structure_type);
+	if (dp_type > 1) {
+		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved dp type value\n",
 			    connector->base.id, connector->name);
-		fallthrough;
-	case 0:
-		info->mso_stream_count = 0;
-		break;
-	case 1:
-		info->mso_stream_count = 2; /* 2 or 4 links */
-		break;
-	case 2:
-		info->mso_stream_count = 4; /* 4 links */
-		break;
+	}
+
+	/* MSO is not supported for eDP */
+	if (dp_type != DISPLAYID_VESA_DP_TYPE_EDP) {
+		switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
+		default:
+			drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
+				    connector->base.id, connector->name);
+			fallthrough;
+		case 0:
+			info->mso_stream_count = 0;
+			break;
+		case 1:
+			info->mso_stream_count = 2; /* 2 or 4 links */
+			break;
+		case 2:
+			info->mso_stream_count = 4; /* 4 links */
+			break;
+		}
 	}
 
 	if (info->mso_stream_count) {
-- 
2.51.2

[PATCH v6 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings

[Yaroslav Bolyukin]

Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 drivers/gpu/drm/drm_displayid_internal.h |  2 ++
 drivers/gpu/drm/drm_edid.c               | 12 ++++++++----
 include/drm/drm_modes.h                  | 10 ++++++++++
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
index 72f107ae832f..724174b429f2 100644
--- a/drivers/gpu/drm/drm_displayid_internal.h
+++ b/drivers/gpu/drm/drm_displayid_internal.h
@@ -97,6 +97,7 @@ struct displayid_header {
 	u8 ext_count;
 } __packed;
 
+#define DISPLAYID_BLOCK_REV	GENMASK(2, 0)
 struct displayid_block {
 	u8 tag;
 	u8 rev;
@@ -125,6 +126,7 @@ struct displayid_detailed_timings_1 {
 	__le16 vsw;
 } __packed;
 
+#define DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT	BIT(3)
 struct displayid_detailed_timing_block {
 	struct displayid_block base;
 	struct displayid_detailed_timings_1 timings[];
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 348aa31aea1b..72a94b1713e2 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6792,8 +6792,8 @@ static void update_display_info(struct drm_connector *connector,
 }
 
 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
-							    const struct displayid_detailed_timings_1 *timings,
-							    bool type_7)
+							    const struct displayid_block *block,
+							    const struct displayid_detailed_timings_1 *timings)
 {
 	struct drm_display_mode *mode;
 	unsigned int pixel_clock = (timings->pixel_clock[0] |
@@ -6809,11 +6809,16 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d
 	unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1;
 	bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15);
 	bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15);
+	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
 
 	mode = drm_mode_create(dev);
 	if (!mode)
 		return NULL;
 
+	if (type_7 && FIELD_GET(DISPLAYID_BLOCK_REV, block->rev) >= 1)
+		mode->dsc_passthrough_timings_support =
+			!!(block->rev & DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT);
+
 	/* resolution is kHz for type VII, and 10 kHz for type I */
 	mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
 	mode->hdisplay = hactive;
@@ -6846,7 +6851,6 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
 	int num_timings;
 	struct drm_display_mode *newmode;
 	int num_modes = 0;
-	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
 	/* blocks must be multiple of 20 bytes length */
 	if (block->num_bytes % 20)
 		return 0;
@@ -6855,7 +6859,7 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
 	for (i = 0; i < num_timings; i++) {
 		struct displayid_detailed_timings_1 *timings = &det->timings[i];
 
-		newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
+		newmode = drm_mode_displayid_detailed(connector->dev, block, timings);
 		if (!newmode)
 			continue;
 
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index b9bb92e4b029..312e5c03af9a 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -417,6 +417,16 @@ struct drm_display_mode {
 	 */
 	enum hdmi_picture_aspect picture_aspect_ratio;
 
+	/**
+	 * @dsc_passthrough_timing_support:
+	 *
+	 * Indicates whether this mode timing descriptor is supported
+	 * with specific target DSC bits per pixel only.
+	 *
+	 * VESA vendor-specific data block shall exist with the relevant
+	 * DSC bits per pixel declaration when this flag is set to true.
+	 */
+	bool dsc_passthrough_timings_support;
 };
 
 /**
-- 
2.51.2

[PATCH v6 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing

[Yaroslav Bolyukin]

Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 drivers/gpu/drm/drm_displayid_internal.h | 1 +
 drivers/gpu/drm/drm_edid.c               | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
index 724174b429f2..55f972d32847 100644
--- a/drivers/gpu/drm/drm_displayid_internal.h
+++ b/drivers/gpu/drm/drm_displayid_internal.h
@@ -139,6 +139,7 @@ struct displayid_formula_timings_9 {
 	u8 vrefresh;
 } __packed;
 
+#define DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES	GENMASK(6, 4)
 struct displayid_formula_timing_block {
 	struct displayid_block base;
 	struct displayid_formula_timings_9 timings[];
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 72a94b1713e2..7bdc99d5084a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6906,7 +6906,8 @@ static int add_displayid_formula_modes(struct drm_connector *connector,
 	struct drm_display_mode *newmode;
 	int num_modes = 0;
 	bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING;
-	int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4);
+	int timing_size = 6 +
+		FIELD_GET(DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES, formula_block->base.rev);
 
 	/* extended blocks are not supported yet */
 	if (timing_size != 6)
-- 
2.51.2

[PATCH v6 6/7] drm/edid: parse DRM VESA dsc bpp target

[Yaroslav Bolyukin]

As per DisplayID v2.1a spec "DSC pass-through timing support",
VESA vendor-specific data block may contain target DSC bits per pixel
fields, that should be always used for the VII modes that declare they
only support working with this value (Pass-through Timing Support for
Target DSC Bits per Pixel).

Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 drivers/gpu/drm/drm_displayid_internal.h |  4 ++++
 drivers/gpu/drm/drm_edid.c               | 16 ++++++++++++++++
 include/drm/drm_connector.h              |  6 ++++++
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
index 55f972d32847..8f1a2f33ca1a 100644
--- a/drivers/gpu/drm/drm_displayid_internal.h
+++ b/drivers/gpu/drm/drm_displayid_internal.h
@@ -148,6 +148,8 @@ struct displayid_formula_timing_block {
 #define DISPLAYID_VESA_DP_TYPE		GENMASK(2, 0)
 #define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
 #define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
+#define DISPLAYID_VESA_DSC_BPP_INT	GENMASK(5, 0)
+#define DISPLAYID_VESA_DSC_BPP_FRACT	GENMASK(3, 0)
 
 #define DISPLAYID_VESA_DP_TYPE_EDP	0
 #define DISPLAYID_VESA_DP_TYPE_DP	1
@@ -157,6 +159,8 @@ struct displayid_vesa_vendor_specific_block {
 	u8 oui[3];
 	u8 data_structure_type;
 	u8 mso;
+	u8 dsc_bpp_int;
+	u8 dsc_bpp_fract;
 } __packed;
 
 /*
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 7bdc99d5084a..b2502be2e807 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6591,6 +6591,21 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
 			    connector->base.id, connector->name,
 			    info->mso_stream_count, info->mso_pixel_overlap);
 	}
+
+	if (block->num_bytes < 7) {
+		/* DSC bpp is optional */
+		return;
+	}
+
+	info->dp_dsc_bpp_x16 = FIELD_GET(DISPLAYID_VESA_DSC_BPP_INT, vesa->dsc_bpp_int) << 4 |
+			       FIELD_GET(DISPLAYID_VESA_DSC_BPP_FRACT, vesa->dsc_bpp_fract);
+
+	if (info->dp_dsc_bpp_x16 > 0) {
+		drm_dbg_kms(connector->dev,
+			    "[CONNECTOR:%d:%s] DSC bits per pixel x16 %u\n",
+			    connector->base.id, connector->name,
+			    info->dp_dsc_bpp_x16);
+	}
 }
 
 static void drm_update_vesa_specific_block(struct drm_connector *connector,
@@ -6639,6 +6654,7 @@ static void drm_reset_display_info(struct drm_connector *connector)
 	info->mso_stream_count = 0;
 	info->mso_pixel_overlap = 0;
 	info->max_dsc_bpp = 0;
+	info->dp_dsc_bpp_x16 = 0;
 
 	kfree(info->vics);
 	info->vics = NULL;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 8f34f4b8183d..7decfc288aa3 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -837,6 +837,12 @@ struct drm_display_info {
 	 */
 	u32 max_dsc_bpp;
 
+	/**
+	 * @dp_dsc_bpp: DP Display-Stream-Compression (DSC) timing's target
+	 * DSC bits per pixel in 6.4 fixed point format. 0 means undefined.
+	 */
+	u16 dp_dsc_bpp_x16;
+
 	/**
 	 * @vics: Array of vics_len VICs. Internal to EDID parsing.
 	 */
-- 
2.51.2

[PATCH v6 7/7] drm/amd: use fixed dsc bits-per-pixel from edid

[Yaroslav Bolyukin]

VESA vendor header from DisplayID spec may contain fixed bit per pixel
rate, it should be used by drm driver for the modes that declare
they are only supported with the declared fixed bits per pixel value.

Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e6728fd12eeb..32370279283f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6613,6 +6613,11 @@ static void fill_stream_properties_from_drm_display_mode(
 
 	stream->output_color_space = get_output_color_space(timing_out, connector_state);
 	stream->content_type = get_output_content_type(connector_state);
+
+	/* DisplayID Type VII pass-through timings. */
+	if (mode_in->dsc_passthrough_timings_support && info->dp_dsc_bpp_x16 != 0) {
+		stream->timing.dsc_fixed_bits_per_pixel_x16 = info->dp_dsc_bpp_x16;
+	}
 }
 
 static void fill_audio_info(struct audio_info *audio_info,
@@ -7071,6 +7076,7 @@ create_stream_for_sink(struct drm_connector *connector,
 	struct drm_display_mode mode;
 	struct drm_display_mode saved_mode;
 	struct drm_display_mode *freesync_mode = NULL;
+	struct drm_display_mode *dsc_passthru_mode = NULL;
 	bool native_mode_found = false;
 	bool recalculate_timing = false;
 	bool scale = dm_state->scaling != RMX_OFF;
@@ -7162,6 +7168,16 @@ create_stream_for_sink(struct drm_connector *connector,
 		}
 	}
 
+	list_for_each_entry(dsc_passthru_mode, &connector->modes, head) {
+		if (dsc_passthru_mode->hdisplay == mode.hdisplay &&
+		    dsc_passthru_mode->vdisplay == mode.vdisplay &&
+		    drm_mode_vrefresh(dsc_passthru_mode) == mode_refresh) {
+			mode.dsc_passthrough_timings_support =
+				dsc_passthru_mode->dsc_passthrough_timings_support;
+			break;
+		}
+	}
+
 	if (recalculate_timing)
 		drm_mode_set_crtcinfo(&saved_mode, 0);
 
-- 
2.51.2

Re: [PATCH v6 0/7] VESA DisplayID spec allows the device to force its DSC bits per pixel value.

[Yaroslav]

Sorry, I have updated/included the wrong cover message

On 2025-11-26 07:51, Yaroslav Bolyukin wrote:
 > For example, the HTC Vive Pro 2 VR headset uses this value in
 > high-resolution modes (3680x1836@90-120, 4896x2448@90-120), and when the
 > kernel doesn't respect this parameter, garbage is displayed on the HMD
 > instead.
 >
 > Me and other users have successfully tested the old (v3) version of this
 > patch (which was applying DSC BPP value unconditionally, thus incorrect:
 > https://lkml.org/lkml/2023/2/26/116) on Vive Pro 2 and
 > Bigscreen Beyond VR headsets, and have been using it daily, it is known
 > to work and doesn't seem to break anything else since 2022.
 >
 > Previously, I didn't have enough dedication to get it merged, I hope
 > this time I will manage to get it to v6.19 :D
 >
 > Regarding driver support - I have looked at amdgpu and Nvidia's
 > open-gpu-kernel-modules, and both seem to have some indication for this
 > value; however, in Linux, it is unused in both.
 >
 > First patch implements parsing of DSC BPP values and display mode VII
 > timings flag which mandates that the DSC BPP value should actually be
 > used for this display mode.

This patch was split into 1-6

 > The second patch implements handling of this value for AMDGPU driver.

This is the 7th patch

 > The only thing that I don't like in the current implementation, is how
 > the value of `dsc_passthrough_timings_support` flag is propagated from
 > the connector display modes to the mode created in 
`DRM_IOCTL_MODE_SETCRTC`
 > handler (which is used for VR display initialization in Monado and
 > StreamVR), it feels like this flag should be initialized by the kernel
 > itself, but as far as I can see there is no correct way to do this, as
 > the timing constraints calculation belongs to the individual drivers.

This is somewhat improved, now there is a matching for correct mode in
amdgpu driver. I don't like that individual drivers need to repeat this
logic by themselves either, but I don't see a better solution with the
given spec and given how it is implemented in devices. It works more
like a quirk, and the implementation follows. It might be improved if
the future changes in DisplayID spec declare something else DSC related
and the logic would be extended appropriately.

Still, the latest implementation should be easy and descriptive enough
to be easily implementable by the drivers, and given that this part of
spec is only used by ~3 devices on the market right now with both being
VR related, I think this is acceptable.

I have a patch somewhat ready for i915, which I decided to not include
in the current patchset, and I don't think there is more drm drivers
that need this implementation right now (Doesn't seem like anyone runs
VR on nouveau).

Since the first version of the patchset was published, nivida open
drivers have implemented this part by themselves, using their own edid
parser.

 > Another problem with how this flag is set, is that there is no hard
 > connection between modes creaded in `SETCRTC` and the modes actually
 > defined by connector, so the current implementation searches for the
 > resolution and refresh rate that match exactly declared to obtain
 > this flag value. This might not be correct, as device might not support
 > the other mode at all, but the situation won't be any worse for the
 > existing devices, as the currently they don't work at all, and there
 > is no other known devices on the market to check their assumption in
 > regard to this part of specs, and the spec does not describe how that
 > should work.
 >
 > Both of those downsides are due to the fact my understanding of DRM
 > subsystem is not that high. If another implementation would be proposed
 > by AMDGPU maintainers - I will gladly implement it here.
 >
 > v5->v6:
 >   * amdgpu: only apply dsc bpp to modes that match exactly the declared
 >     modes with this flag set.
 > v4->v5:
 >   * The patch was split into multiple
 >   * Disabled MSO parsing for eDP displays
 >   * Disabled MSO logs if not used
 >   * Minor codestyle changes: lines moved around, naming, passing of
 >     function arguments
 > v3->v4:
 >   * This patch now parses timings support flag on type VII block, instead
 >     of applying it unconditionally. Previously I didn't understand the
 >     spec properly.
 >   * Now it also is not being applied for non-supported and/or non-VII
 >     blocks in amdgpu driver.
 >
 > Regards,
 >
 > Lach
 >
 > Yaroslav Bolyukin (7):
 >    drm/edid: rename VESA block parsing functions to more generic name
 >    drm/edid: prepare for VESA vendor-specific data block extension
 >    drm/edid: MSO should only be used for non-eDP displays
 >    drm/edid: parse DSC DPP passthru support flag for mode VII timings
 >    drm/edid: for consistency, use mask everywhere for block rev parsing
 >    drm/edid: parse DRM VESA dsc bpp target
 >    drm/amd: use fixed dsc bits-per-pixel from edid
 >
 >   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  16 +++
 >   drivers/gpu/drm/drm_displayid_internal.h      |  11 ++
 >   drivers/gpu/drm/drm_edid.c                    | 101 +++++++++++-------
 >   include/drm/drm_connector.h                   |   6 ++
 >   include/drm/drm_modes.h                       |  10 ++
 >   5 files changed, 107 insertions(+), 37 deletions(-)
 >

Re: [PATCH v6 1/7] drm/edid: rename VESA block parsing functions to more generic name

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> Those functions would also parse DSC Bits Per Pixel value in the future
> commits.
>
> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/drm_edid.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 26bb7710a462..64f7a94dd9e4 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6527,8 +6527,8 @@ static void drm_get_monitor_range(struct drm_connector *connector,
>  		    info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
>  }
>  
> -static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> -				    const struct displayid_block *block)
> +static void drm_parse_vesa_specific_block(struct drm_connector *connector,
> +					  const struct displayid_block *block)
>  {
>  	struct displayid_vesa_vendor_specific_block *vesa =
>  		(struct displayid_vesa_vendor_specific_block *)block;
> @@ -6587,8 +6587,8 @@ static void drm_parse_vesa_mso_data(struct drm_connector *connector,
>  		    info->mso_stream_count, info->mso_pixel_overlap);
>  }
>  
> -static void drm_update_mso(struct drm_connector *connector,
> -			   const struct drm_edid *drm_edid)
> +static void drm_update_vesa_specific_block(struct drm_connector *connector,
> +					   const struct drm_edid *drm_edid)
>  {
>  	const struct displayid_block *block;
>  	struct displayid_iter iter;
> @@ -6596,7 +6596,7 @@ static void drm_update_mso(struct drm_connector *connector,
>  	displayid_iter_edid_begin(drm_edid, &iter);
>  	displayid_iter_for_each(block, &iter) {
>  		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
> -			drm_parse_vesa_mso_data(connector, block);
> +			drm_parse_vesa_specific_block(connector, block);
>  	}
>  	displayid_iter_end(&iter);
>  }
> @@ -6756,7 +6756,7 @@ static void update_display_info(struct drm_connector *connector,
>  	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
>  		info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
>  
> -	drm_update_mso(connector, drm_edid);
> +	drm_update_vesa_specific_block(connector, drm_edid);
>  
>  out:
>  	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_NON_DESKTOP)) {

-- 
Jani Nikula, Intel

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> Current VESA vendor-specific block parsing expects real block size to be
> the same as the defined struct size, use real offsets in conditionals
> instead to add struct fields in future commits.
>
> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>

I think this is something we want to backport, since MSO would break
with bigger vendor-specific blocks, and that leads to black screens on
MSO displays.

Cc: stable@vger.kernel.org
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
>  1 file changed, 12 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 64f7a94dd9e4..a52fd6de9327 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>  	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>  		return;
>  
> -	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
> +	if (block->num_bytes < 5) {
>  		drm_dbg_kms(connector->dev,
>  			    "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
>  			    connector->base.id, connector->name);
> @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>  		break;
>  	}
>  
> -	if (!info->mso_stream_count) {
> -		info->mso_pixel_overlap = 0;
> -		return;
> -	}
> -
> -	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
> -	if (info->mso_pixel_overlap > 8) {
> +	if (info->mso_stream_count) {
> +		info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
> +		if (info->mso_pixel_overlap > 8) {
> +			drm_dbg_kms(connector->dev,
> +				    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
> +				    connector->base.id, connector->name,
> +				    info->mso_pixel_overlap);
> +			info->mso_pixel_overlap = 8;
> +		}
>  		drm_dbg_kms(connector->dev,
> -			    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
> +			    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>  			    connector->base.id, connector->name,
> -			    info->mso_pixel_overlap);
> -		info->mso_pixel_overlap = 8;
> +			    info->mso_stream_count, info->mso_pixel_overlap);
>  	}
> -
> -	drm_dbg_kms(connector->dev,
> -		    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
> -		    connector->base.id, connector->name,
> -		    info->mso_stream_count, info->mso_pixel_overlap);
>  }
>  
>  static void drm_update_vesa_specific_block(struct drm_connector *connector,

-- 
Jani Nikula, Intel

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Jani Nikula]

On Wed, 26 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>> Current VESA vendor-specific block parsing expects real block size to be
>> the same as the defined struct size, use real offsets in conditionals
>> instead to add struct fields in future commits.
>>
>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>
> I think this is something we want to backport, since MSO would break
> with bigger vendor-specific blocks, and that leads to black screens on
> MSO displays.
>
> Cc: stable@vger.kernel.org
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Oops, I'll take that back.

>
>> ---
>>  drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
>>  1 file changed, 12 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index 64f7a94dd9e4..a52fd6de9327 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>  	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>>  		return;
>>  
>> -	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>> +	if (block->num_bytes < 5) {
>>  		drm_dbg_kms(connector->dev,
>>  			    "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
>>  			    connector->base.id, connector->name);
>> @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>  		break;
>>  	}
>>  
>> -	if (!info->mso_stream_count) {
>> -		info->mso_pixel_overlap = 0;

This is no longer cleared for !info->mso_stream_count.

Perhaps the code could be reorganized to handle it better.

>> -		return;
>> -	}
>> -
>> -	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>> -	if (info->mso_pixel_overlap > 8) {
>> +	if (info->mso_stream_count) {
>> +		info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>> +		if (info->mso_pixel_overlap > 8) {
>> +			drm_dbg_kms(connector->dev,
>> +				    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>> +				    connector->base.id, connector->name,
>> +				    info->mso_pixel_overlap);
>> +			info->mso_pixel_overlap = 8;
>> +		}
>>  		drm_dbg_kms(connector->dev,
>> -			    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>> +			    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>  			    connector->base.id, connector->name,
>> -			    info->mso_pixel_overlap);
>> -		info->mso_pixel_overlap = 8;
>> +			    info->mso_stream_count, info->mso_pixel_overlap);
>>  	}
>> -
>> -	drm_dbg_kms(connector->dev,
>> -		    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>> -		    connector->base.id, connector->name,
>> -		    info->mso_stream_count, info->mso_pixel_overlap);
>>  }
>>  
>>  static void drm_update_vesa_specific_block(struct drm_connector *connector,

-- 
Jani Nikula, Intel

Re: [PATCH v6 3/7] drm/edid: MSO should only be used for non-eDP displays

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> As per DisplayID v2.1a spec:
> If Offset 06h[2:0] is programmed to 001b (External DisplayPort), this
> field shall be cleared to 00b (Not supported).
>
> Link: https://lore.kernel.org/lkml/3abc1087618c822e5676e67a3ec2e64e506dc5ec@intel.com/
> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
> ---
>  drivers/gpu/drm/drm_displayid_internal.h |  4 +++
>  drivers/gpu/drm/drm_edid.c               | 36 +++++++++++++++---------
>  2 files changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
> index 5b1b32f73516..72f107ae832f 100644
> --- a/drivers/gpu/drm/drm_displayid_internal.h
> +++ b/drivers/gpu/drm/drm_displayid_internal.h
> @@ -142,9 +142,13 @@ struct displayid_formula_timing_block {
>  	struct displayid_formula_timings_9 timings[];
>  } __packed;
>  
> +#define DISPLAYID_VESA_DP_TYPE		GENMASK(2, 0)
>  #define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
>  #define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
>  
> +#define DISPLAYID_VESA_DP_TYPE_EDP	0
> +#define DISPLAYID_VESA_DP_TYPE_DP	1
> +
>  struct displayid_vesa_vendor_specific_block {
>  	struct displayid_block base;
>  	u8 oui[3];
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index a52fd6de9327..348aa31aea1b 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6533,6 +6533,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>  	struct displayid_vesa_vendor_specific_block *vesa =
>  		(struct displayid_vesa_vendor_specific_block *)block;
>  	struct drm_display_info *info = &connector->display_info;
> +	int dp_type;
>  
>  	if (block->num_bytes < 3) {
>  		drm_dbg_kms(connector->dev,
> @@ -6551,20 +6552,29 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>  		return;
>  	}
>  
> -	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> -	default:
> -		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
> +	dp_type = FIELD_GET(DISPLAYID_VESA_DP_TYPE, vesa->data_structure_type);
> +	if (dp_type > 1) {
> +		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved dp type value\n",
>  			    connector->base.id, connector->name);
> -		fallthrough;
> -	case 0:
> -		info->mso_stream_count = 0;
> -		break;
> -	case 1:
> -		info->mso_stream_count = 2; /* 2 or 4 links */
> -		break;
> -	case 2:
> -		info->mso_stream_count = 4; /* 4 links */
> -		break;
> +	}
> +
> +	/* MSO is not supported for eDP */
> +	if (dp_type != DISPLAYID_VESA_DP_TYPE_EDP) {

MSO is *only* supported on eDP, not the other way round!

BR,
Jani.

> +		switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> +		default:
> +			drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
> +				    connector->base.id, connector->name);
> +			fallthrough;
> +		case 0:
> +			info->mso_stream_count = 0;
> +			break;
> +		case 1:
> +			info->mso_stream_count = 2; /* 2 or 4 links */
> +			break;
> +		case 2:
> +			info->mso_stream_count = 4; /* 4 links */
> +			break;
> +		}
>  	}
>  
>  	if (info->mso_stream_count) {

-- 
Jani Nikula, Intel

Re: [PATCH v6 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:

The commit message goes here.

> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
> ---
>  drivers/gpu/drm/drm_displayid_internal.h |  2 ++
>  drivers/gpu/drm/drm_edid.c               | 12 ++++++++----
>  include/drm/drm_modes.h                  | 10 ++++++++++
>  3 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
> index 72f107ae832f..724174b429f2 100644
> --- a/drivers/gpu/drm/drm_displayid_internal.h
> +++ b/drivers/gpu/drm/drm_displayid_internal.h
> @@ -97,6 +97,7 @@ struct displayid_header {
>  	u8 ext_count;
>  } __packed;
>  
> +#define DISPLAYID_BLOCK_REV	GENMASK(2, 0)
>  struct displayid_block {
>  	u8 tag;
>  	u8 rev;
> @@ -125,6 +126,7 @@ struct displayid_detailed_timings_1 {
>  	__le16 vsw;
>  } __packed;
>  
> +#define DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT	BIT(3)
>  struct displayid_detailed_timing_block {
>  	struct displayid_block base;
>  	struct displayid_detailed_timings_1 timings[];
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 348aa31aea1b..72a94b1713e2 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6792,8 +6792,8 @@ static void update_display_info(struct drm_connector *connector,
>  }
>  
>  static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
> -							    const struct displayid_detailed_timings_1 *timings,
> -							    bool type_7)
> +							    const struct displayid_block *block,
> +							    const struct displayid_detailed_timings_1 *timings)
>  {
>  	struct drm_display_mode *mode;
>  	unsigned int pixel_clock = (timings->pixel_clock[0] |
> @@ -6809,11 +6809,16 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d
>  	unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1;
>  	bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15);
>  	bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15);
> +	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
>  
>  	mode = drm_mode_create(dev);
>  	if (!mode)
>  		return NULL;
>  
> +	if (type_7 && FIELD_GET(DISPLAYID_BLOCK_REV, block->rev) >= 1)
> +		mode->dsc_passthrough_timings_support =
> +			!!(block->rev & DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT);

The !! and parentheses are superfluous.

> +
>  	/* resolution is kHz for type VII, and 10 kHz for type I */
>  	mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
>  	mode->hdisplay = hactive;
> @@ -6846,7 +6851,6 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
>  	int num_timings;
>  	struct drm_display_mode *newmode;
>  	int num_modes = 0;
> -	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
>  	/* blocks must be multiple of 20 bytes length */
>  	if (block->num_bytes % 20)
>  		return 0;
> @@ -6855,7 +6859,7 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
>  	for (i = 0; i < num_timings; i++) {
>  		struct displayid_detailed_timings_1 *timings = &det->timings[i];
>  
> -		newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
> +		newmode = drm_mode_displayid_detailed(connector->dev, block, timings);
>  		if (!newmode)
>  			continue;
>  
> diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
> index b9bb92e4b029..312e5c03af9a 100644
> --- a/include/drm/drm_modes.h
> +++ b/include/drm/drm_modes.h
> @@ -417,6 +417,16 @@ struct drm_display_mode {
>  	 */
>  	enum hdmi_picture_aspect picture_aspect_ratio;
>  
> +	/**
> +	 * @dsc_passthrough_timing_support:
> +	 *
> +	 * Indicates whether this mode timing descriptor is supported
> +	 * with specific target DSC bits per pixel only.
> +	 *
> +	 * VESA vendor-specific data block shall exist with the relevant
> +	 * DSC bits per pixel declaration when this flag is set to true.
> +	 */
> +	bool dsc_passthrough_timings_support;
>  };
>  
>  /**

-- 
Jani Nikula, Intel

Re: [PATCH v6 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:

Commit message goes here.

> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
> ---
>  drivers/gpu/drm/drm_displayid_internal.h | 1 +
>  drivers/gpu/drm/drm_edid.c               | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
> index 724174b429f2..55f972d32847 100644
> --- a/drivers/gpu/drm/drm_displayid_internal.h
> +++ b/drivers/gpu/drm/drm_displayid_internal.h
> @@ -139,6 +139,7 @@ struct displayid_formula_timings_9 {
>  	u8 vrefresh;
>  } __packed;
>  
> +#define DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES	GENMASK(6, 4)
>  struct displayid_formula_timing_block {
>  	struct displayid_block base;
>  	struct displayid_formula_timings_9 timings[];
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 72a94b1713e2..7bdc99d5084a 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6906,7 +6906,8 @@ static int add_displayid_formula_modes(struct drm_connector *connector,
>  	struct drm_display_mode *newmode;
>  	int num_modes = 0;
>  	bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING;
> -	int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4);
> +	int timing_size = 6 +
> +		FIELD_GET(DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES, formula_block->base.rev);
>  
>  	/* extended blocks are not supported yet */
>  	if (timing_size != 6)

-- 
Jani Nikula, Intel

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Yaroslav]

On 2025-11-26 10:13, Jani Nikula wrote:
> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>> Current VESA vendor-specific block parsing expects real block size to be
>> the same as the defined struct size, use real offsets in conditionals
>> instead to add struct fields in future commits.
>>
>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
> 
> I think this is something we want to backport, since MSO would break
> with bigger vendor-specific blocks, and that leads to black screens on
> MSO displays.
> 

Not sure why would we want to backport that if we don't backport the 
other changes, old kernels will just have the broken implementation, 
which in reality affects almost no body, given that there were no bug 
reports
> Cc: stable@vger.kernel.org
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
>> ---
>>   drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
>>   1 file changed, 12 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index 64f7a94dd9e4..a52fd6de9327 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>   	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>>   		return;
>>   
>> -	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>> +	if (block->num_bytes < 5) {
>>   		drm_dbg_kms(connector->dev,
>>   			    "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
>>   			    connector->base.id, connector->name);
>> @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>   		break;
>>   	}
>>   
>> -	if (!info->mso_stream_count) {
>> -		info->mso_pixel_overlap = 0;
>> -		return;
>> -	}
>> -
>> -	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>> -	if (info->mso_pixel_overlap > 8) {
>> +	if (info->mso_stream_count) {
>> +		info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>> +		if (info->mso_pixel_overlap > 8) {
>> +			drm_dbg_kms(connector->dev,
>> +				    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>> +				    connector->base.id, connector->name,
>> +				    info->mso_pixel_overlap);
>> +			info->mso_pixel_overlap = 8;
>> +		}
>>   		drm_dbg_kms(connector->dev,
>> -			    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>> +			    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>   			    connector->base.id, connector->name,
>> -			    info->mso_pixel_overlap);
>> -		info->mso_pixel_overlap = 8;
>> +			    info->mso_stream_count, info->mso_pixel_overlap);
>>   	}
>> -
>> -	drm_dbg_kms(connector->dev,
>> -		    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>> -		    connector->base.id, connector->name,
>> -		    info->mso_stream_count, info->mso_pixel_overlap);
>>   }
>>   
>>   static void drm_update_vesa_specific_block(struct drm_connector *connector,
> 

Re: [PATCH v6 3/7] drm/edid: MSO should only be used for non-eDP displays

[Yaroslav]

On 2025-11-26 15:10, Jani Nikula wrote:
> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>> As per DisplayID v2.1a spec:
>> If Offset 06h[2:0] is programmed to 001b (External DisplayPort), this
>> field shall be cleared to 00b (Not supported).
>>
>> Link: https://lore.kernel.org/lkml/3abc1087618c822e5676e67a3ec2e64e506dc5ec@intel.com/
>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>> ---
>>   drivers/gpu/drm/drm_displayid_internal.h |  4 +++
>>   drivers/gpu/drm/drm_edid.c               | 36 +++++++++++++++---------
>>   2 files changed, 27 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
>> index 5b1b32f73516..72f107ae832f 100644
>> --- a/drivers/gpu/drm/drm_displayid_internal.h
>> +++ b/drivers/gpu/drm/drm_displayid_internal.h
>> @@ -142,9 +142,13 @@ struct displayid_formula_timing_block {
>>   	struct displayid_formula_timings_9 timings[];
>>   } __packed;
>>   
>> +#define DISPLAYID_VESA_DP_TYPE		GENMASK(2, 0)
>>   #define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
>>   #define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
>>   
>> +#define DISPLAYID_VESA_DP_TYPE_EDP	0
>> +#define DISPLAYID_VESA_DP_TYPE_DP	1
>> +
>>   struct displayid_vesa_vendor_specific_block {
>>   	struct displayid_block base;
>>   	u8 oui[3];
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index a52fd6de9327..348aa31aea1b 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -6533,6 +6533,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>   	struct displayid_vesa_vendor_specific_block *vesa =
>>   		(struct displayid_vesa_vendor_specific_block *)block;
>>   	struct drm_display_info *info = &connector->display_info;
>> +	int dp_type;
>>   
>>   	if (block->num_bytes < 3) {
>>   		drm_dbg_kms(connector->dev,
>> @@ -6551,20 +6552,29 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>   		return;
>>   	}
>>   
>> -	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
>> -	default:
>> -		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
>> +	dp_type = FIELD_GET(DISPLAYID_VESA_DP_TYPE, vesa->data_structure_type);
>> +	if (dp_type > 1) {
>> +		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved dp type value\n",
>>   			    connector->base.id, connector->name);
>> -		fallthrough;
>> -	case 0:
>> -		info->mso_stream_count = 0;
>> -		break;
>> -	case 1:
>> -		info->mso_stream_count = 2; /* 2 or 4 links */
>> -		break;
>> -	case 2:
>> -		info->mso_stream_count = 4; /* 4 links */
>> -		break;
>> +	}
>> +
>> +	/* MSO is not supported for eDP */
>> +	if (dp_type != DISPLAYID_VESA_DP_TYPE_EDP) {
> 
> MSO is *only* supported on eDP, not the other way round!
> 
> BR,
> Jani.
> 

Oh, yes. For some reason I thought that MSO == MST, and it made no sense 
for me why would MST be only supported on eDP, I see now that this is a 
separate thing. I should probably don't include this patch in the 
patchset, since this is the only part that I don't have hardware to test

>> +		switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
>> +		default:
>> +			drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
>> +				    connector->base.id, connector->name);
>> +			fallthrough;
>> +		case 0:
>> +			info->mso_stream_count = 0;
>> +			break;
>> +		case 1:
>> +			info->mso_stream_count = 2; /* 2 or 4 links */
>> +			break;
>> +		case 2:
>> +			info->mso_stream_count = 4; /* 4 links */
>> +			break;
>> +		}
>>   	}
>>   
>>   	if (info->mso_stream_count) {
> 

Re: [PATCH v6 6/7] drm/edid: parse DRM VESA dsc bpp target

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> As per DisplayID v2.1a spec "DSC pass-through timing support",
> VESA vendor-specific data block may contain target DSC bits per pixel
> fields, that should be always used for the VII modes that declare they
> only support working with this value (Pass-through Timing Support for
> Target DSC Bits per Pixel).
>
> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
> ---
>  drivers/gpu/drm/drm_displayid_internal.h |  4 ++++
>  drivers/gpu/drm/drm_edid.c               | 16 ++++++++++++++++
>  include/drm/drm_connector.h              |  6 ++++++
>  3 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
> index 55f972d32847..8f1a2f33ca1a 100644
> --- a/drivers/gpu/drm/drm_displayid_internal.h
> +++ b/drivers/gpu/drm/drm_displayid_internal.h
> @@ -148,6 +148,8 @@ struct displayid_formula_timing_block {
>  #define DISPLAYID_VESA_DP_TYPE		GENMASK(2, 0)
>  #define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
>  #define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
> +#define DISPLAYID_VESA_DSC_BPP_INT	GENMASK(5, 0)
> +#define DISPLAYID_VESA_DSC_BPP_FRACT	GENMASK(3, 0)
>  
>  #define DISPLAYID_VESA_DP_TYPE_EDP	0
>  #define DISPLAYID_VESA_DP_TYPE_DP	1
> @@ -157,6 +159,8 @@ struct displayid_vesa_vendor_specific_block {
>  	u8 oui[3];
>  	u8 data_structure_type;
>  	u8 mso;
> +	u8 dsc_bpp_int;
> +	u8 dsc_bpp_fract;
>  } __packed;
>  
>  /*
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 7bdc99d5084a..b2502be2e807 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6591,6 +6591,21 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>  			    connector->base.id, connector->name,
>  			    info->mso_stream_count, info->mso_pixel_overlap);
>  	}
> +
> +	if (block->num_bytes < 7) {
> +		/* DSC bpp is optional */
> +		return;
> +	}
> +
> +	info->dp_dsc_bpp_x16 = FIELD_GET(DISPLAYID_VESA_DSC_BPP_INT, vesa->dsc_bpp_int) << 4 |
> +			       FIELD_GET(DISPLAYID_VESA_DSC_BPP_FRACT, vesa->dsc_bpp_fract);
> +
> +	if (info->dp_dsc_bpp_x16 > 0) {
> +		drm_dbg_kms(connector->dev,
> +			    "[CONNECTOR:%d:%s] DSC bits per pixel x16 %u\n",
> +			    connector->base.id, connector->name,
> +			    info->dp_dsc_bpp_x16);

Use drm_fixed.h, and do something like this:

	drm_dbg_kms(connector->dev,
		    "[CONNECTOR:%d:%s] DSC bits per pixel " FXP_Q4_FMT "\n",
		    connector->base.id, connector->name,
		    FXP_Q4_ARGS(info->dp_dsc_bpp_x16));

and you'll get the actual x.y in the output.


> +	}
>  }
>  
>  static void drm_update_vesa_specific_block(struct drm_connector *connector,
> @@ -6639,6 +6654,7 @@ static void drm_reset_display_info(struct drm_connector *connector)
>  	info->mso_stream_count = 0;
>  	info->mso_pixel_overlap = 0;
>  	info->max_dsc_bpp = 0;
> +	info->dp_dsc_bpp_x16 = 0;
>  
>  	kfree(info->vics);
>  	info->vics = NULL;
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 8f34f4b8183d..7decfc288aa3 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -837,6 +837,12 @@ struct drm_display_info {
>  	 */
>  	u32 max_dsc_bpp;
>  
> +	/**
> +	 * @dp_dsc_bpp: DP Display-Stream-Compression (DSC) timing's target
> +	 * DSC bits per pixel in 6.4 fixed point format. 0 means undefined.
> +	 */
> +	u16 dp_dsc_bpp_x16;
> +
>  	/**
>  	 * @vics: Array of vics_len VICs. Internal to EDID parsing.
>  	 */

-- 
Jani Nikula, Intel

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
> On 2025-11-26 10:13, Jani Nikula wrote:
>> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>>> Current VESA vendor-specific block parsing expects real block size to be
>>> the same as the defined struct size, use real offsets in conditionals
>>> instead to add struct fields in future commits.
>>>
>>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>> 
>> I think this is something we want to backport, since MSO would break
>> with bigger vendor-specific blocks, and that leads to black screens on
>> MSO displays.
>> 
>
> Not sure why would we want to backport that if we don't backport the 
> other changes, old kernels will just have the broken implementation, 
> which in reality affects almost no body, given that there were no bug 
> reports

The failure mode is: Someone buys a new shiny laptop with eDP MSO, with
bigger vendor block, and won't get a picture on screen.

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH v6 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings

[Yaroslav]

On 2025-11-26 15:19, Jani Nikula wrote:
> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> 
> The commit message goes here.
> 
>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>> ---
>>   drivers/gpu/drm/drm_displayid_internal.h |  2 ++
>>   drivers/gpu/drm/drm_edid.c               | 12 ++++++++----
>>   include/drm/drm_modes.h                  | 10 ++++++++++
>>   3 files changed, 20 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
>> index 72f107ae832f..724174b429f2 100644
>> --- a/drivers/gpu/drm/drm_displayid_internal.h
>> +++ b/drivers/gpu/drm/drm_displayid_internal.h
>> @@ -97,6 +97,7 @@ struct displayid_header {
>>   	u8 ext_count;
>>   } __packed;
>>   
>> +#define DISPLAYID_BLOCK_REV	GENMASK(2, 0)
>>   struct displayid_block {
>>   	u8 tag;
>>   	u8 rev;
>> @@ -125,6 +126,7 @@ struct displayid_detailed_timings_1 {
>>   	__le16 vsw;
>>   } __packed;
>>   
>> +#define DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT	BIT(3)
>>   struct displayid_detailed_timing_block {
>>   	struct displayid_block base;
>>   	struct displayid_detailed_timings_1 timings[];
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index 348aa31aea1b..72a94b1713e2 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -6792,8 +6792,8 @@ static void update_display_info(struct drm_connector *connector,
>>   }
>>   
>>   static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
>> -							    const struct displayid_detailed_timings_1 *timings,
>> -							    bool type_7)
>> +							    const struct displayid_block *block,
>> +							    const struct displayid_detailed_timings_1 *timings)
>>   {
>>   	struct drm_display_mode *mode;
>>   	unsigned int pixel_clock = (timings->pixel_clock[0] |
>> @@ -6809,11 +6809,16 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d
>>   	unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1;
>>   	bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15);
>>   	bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15);
>> +	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
>>   
>>   	mode = drm_mode_create(dev);
>>   	if (!mode)
>>   		return NULL;
>>   
>> +	if (type_7 && FIELD_GET(DISPLAYID_BLOCK_REV, block->rev) >= 1)
>> +		mode->dsc_passthrough_timings_support =
>> +			!!(block->rev & DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT);
> 
> The !! and parentheses are superfluous.
> 

Most of the other instances of bitflag parsing logic in kernel seem to 
cast integers to booleans explicitly this way.

I'm fine with simplifying that, I was only doing what everyone else does.

>> +
>>   	/* resolution is kHz for type VII, and 10 kHz for type I */
>>   	mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
>>   	mode->hdisplay = hactive;
>> @@ -6846,7 +6851,6 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
>>   	int num_timings;
>>   	struct drm_display_mode *newmode;
>>   	int num_modes = 0;
>> -	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
>>   	/* blocks must be multiple of 20 bytes length */
>>   	if (block->num_bytes % 20)
>>   		return 0;
>> @@ -6855,7 +6859,7 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
>>   	for (i = 0; i < num_timings; i++) {
>>   		struct displayid_detailed_timings_1 *timings = &det->timings[i];
>>   
>> -		newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
>> +		newmode = drm_mode_displayid_detailed(connector->dev, block, timings);
>>   		if (!newmode)
>>   			continue;
>>   
>> diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
>> index b9bb92e4b029..312e5c03af9a 100644
>> --- a/include/drm/drm_modes.h
>> +++ b/include/drm/drm_modes.h
>> @@ -417,6 +417,16 @@ struct drm_display_mode {
>>   	 */
>>   	enum hdmi_picture_aspect picture_aspect_ratio;
>>   
>> +	/**
>> +	 * @dsc_passthrough_timing_support:
>> +	 *
>> +	 * Indicates whether this mode timing descriptor is supported
>> +	 * with specific target DSC bits per pixel only.
>> +	 *
>> +	 * VESA vendor-specific data block shall exist with the relevant
>> +	 * DSC bits per pixel declaration when this flag is set to true.
>> +	 */
>> +	bool dsc_passthrough_timings_support;
>>   };
>>   
>>   /**
> 

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Yaroslav]

On 2025-11-26 15:29, Jani Nikula wrote:
> On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
> The failure mode is: Someone buys a new shiny laptop with eDP MSO, with
> bigger vendor block, and won't get a picture on screen.

I understand that, I'm only confused because this does seem to be as 
suitable for backport as this fixed DSC bpp thing is:

Someone buys a VR headset with fixed DSC bpp (Bigscreen Beyond/Bigscreen 
Beyond 2/Vive Pro 2), and the system is unable to detect them.

Unless eDP MSO with vendor specific data block extended with unset fixed 
DSC bpp value is much more popular in the wild, that is. I have however 
failed to discover any devices which have this value present other than 
the three mentioned VR headsets.

> BR,
> Jani.
> 
> 

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
> On 2025-11-26 15:29, Jani Nikula wrote:
>> On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
>> The failure mode is: Someone buys a new shiny laptop with eDP MSO, with
>> bigger vendor block, and won't get a picture on screen.
>
> I understand that, I'm only confused because this does seem to be as 
> suitable for backport as this fixed DSC bpp thing is:
>
> Someone buys a VR headset with fixed DSC bpp (Bigscreen Beyond/Bigscreen 
> Beyond 2/Vive Pro 2), and the system is unable to detect them.
>
> Unless eDP MSO with vendor specific data block extended with unset fixed 
> DSC bpp value is much more popular in the wild, that is. I have however 
> failed to discover any devices which have this value present other than 
> the three mentioned VR headsets.

The difference is between an existing and enabled feature working vs. a
new feature working. eDP MSO is expected to work. Also, IIUC you can
still use the VR headsets albeit with a lower resolution. For eDP MSO
you simply get nothing, and even beginning to debug the issue is
problematic, since that is quite possibly the only display on the
device.


BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Yaroslav]

On 2025-11-26 15:08, Jani Nikula wrote:
> On Wed, 26 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>>> Current VESA vendor-specific block parsing expects real block size to be
>>> the same as the defined struct size, use real offsets in conditionals
>>> instead to add struct fields in future commits.
>>>
>>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>>
>> I think this is something we want to backport, since MSO would break
>> with bigger vendor-specific blocks, and that leads to black screens on
>> MSO displays.
>>
>> Cc: stable@vger.kernel.org
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> Oops, I'll take that back.
> 
>>
>>> ---
>>>   drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
>>>   1 file changed, 12 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>>> index 64f7a94dd9e4..a52fd6de9327 100644
>>> --- a/drivers/gpu/drm/drm_edid.c
>>> +++ b/drivers/gpu/drm/drm_edid.c
>>> @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>   	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>>>   		return;
>>>   
>>> -	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>>> +	if (block->num_bytes < 5) {
>>>   		drm_dbg_kms(connector->dev,
>>>   			    "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
>>>   			    connector->base.id, connector->name);
>>> @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>   		break;
>>>   	}
>>>   
>>> -	if (!info->mso_stream_count) {
>>> -		info->mso_pixel_overlap = 0;
> 
> This is no longer cleared for !info->mso_stream_count.
> 
> Perhaps the code could be reorganized to handle it better.

It defaults to zero due to drm_reset_display_info()

>>> -		return;
>>> -	}
>>> -
>>> -	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>> -	if (info->mso_pixel_overlap > 8) {
>>> +	if (info->mso_stream_count) {
>>> +		info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>> +		if (info->mso_pixel_overlap > 8) {
>>> +			drm_dbg_kms(connector->dev,
>>> +				    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>>> +				    connector->base.id, connector->name,
>>> +				    info->mso_pixel_overlap);
>>> +			info->mso_pixel_overlap = 8;
>>> +		}
>>>   		drm_dbg_kms(connector->dev,
>>> -			    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>>> +			    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>>   			    connector->base.id, connector->name,
>>> -			    info->mso_pixel_overlap);
>>> -		info->mso_pixel_overlap = 8;
>>> +			    info->mso_stream_count, info->mso_pixel_overlap);
>>>   	}
>>> -
>>> -	drm_dbg_kms(connector->dev,
>>> -		    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>> -		    connector->base.id, connector->name,
>>> -		    info->mso_stream_count, info->mso_pixel_overlap);
>>>   }
>>>   
>>>   static void drm_update_vesa_specific_block(struct drm_connector *connector,
> 

Re: [PATCH v6 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
> On 2025-11-26 15:19, Jani Nikula wrote:
>> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>>> +	if (type_7 && FIELD_GET(DISPLAYID_BLOCK_REV, block->rev) >= 1)
>>> +		mode->dsc_passthrough_timings_support =
>>> +			!!(block->rev & DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT);
>> 
>> The !! and parentheses are superfluous.
>> 
>
> Most of the other instances of bitflag parsing logic in kernel seem to 
> cast integers to booleans explicitly this way.
>
> I'm fine with simplifying that, I was only doing what everyone else does.

I get that, but such habits originate from the days before std bool. !!
normalizes ints to 0 and 1, but assigning to bool does the same for you.

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Yaroslav]

On 2025-11-26 15:47, Jani Nikula wrote:
> On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
>> On 2025-11-26 15:29, Jani Nikula wrote:
>>> On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
>>> The failure mode is: Someone buys a new shiny laptop with eDP MSO, with
>>> bigger vendor block, and won't get a picture on screen.
>>
>> I understand that, I'm only confused because this does seem to be as
>> suitable for backport as this fixed DSC bpp thing is:
>>
>> Someone buys a VR headset with fixed DSC bpp (Bigscreen Beyond/Bigscreen
>> Beyond 2/Vive Pro 2), and the system is unable to detect them.
>>
>> Unless eDP MSO with vendor specific data block extended with unset fixed
>> DSC bpp value is much more popular in the wild, that is. I have however
>> failed to discover any devices which have this value present other than
>> the three mentioned VR headsets.
> 
> The difference is between an existing and enabled feature working vs. a
> new feature working. eDP MSO is expected to work. Also, IIUC you can
> still use the VR headsets albeit with a lower resolution. For eDP MSO
> you simply get nothing, and even beginning to debug the issue is
> problematic, since that is quite possibly the only display on the
> device.
> 

You can use Vive Pro 2 with a lower resolution, but there is no lower 
resolution option present for BSB/BSB2, their support is always borked 
without this patch, and they are more popular in the linux community.

> 
> BR,
> Jani.
> 
> 

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
> On 2025-11-26 15:08, Jani Nikula wrote:
>> On Wed, 26 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>>>> Current VESA vendor-specific block parsing expects real block size to be
>>>> the same as the defined struct size, use real offsets in conditionals
>>>> instead to add struct fields in future commits.
>>>>
>>>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>>>
>>> I think this is something we want to backport, since MSO would break
>>> with bigger vendor-specific blocks, and that leads to black screens on
>>> MSO displays.
>>>
>>> Cc: stable@vger.kernel.org
>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> Oops, I'll take that back.
>> 
>>>
>>>> ---
>>>>   drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
>>>>   1 file changed, 12 insertions(+), 16 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>>>> index 64f7a94dd9e4..a52fd6de9327 100644
>>>> --- a/drivers/gpu/drm/drm_edid.c
>>>> +++ b/drivers/gpu/drm/drm_edid.c
>>>> @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>>   	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>>>>   		return;
>>>>   
>>>> -	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>>>> +	if (block->num_bytes < 5) {
>>>>   		drm_dbg_kms(connector->dev,
>>>>   			    "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
>>>>   			    connector->base.id, connector->name);
>>>> @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>>   		break;
>>>>   	}
>>>>   
>>>> -	if (!info->mso_stream_count) {
>>>> -		info->mso_pixel_overlap = 0;
>> 
>> This is no longer cleared for !info->mso_stream_count.
>> 
>> Perhaps the code could be reorganized to handle it better.
>
> It defaults to zero due to drm_reset_display_info()

Yes, and the code above the context initializes it from the vendor
block.


>
>>>> -		return;
>>>> -	}
>>>> -
>>>> -	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>>> -	if (info->mso_pixel_overlap > 8) {
>>>> +	if (info->mso_stream_count) {
>>>> +		info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>>> +		if (info->mso_pixel_overlap > 8) {
>>>> +			drm_dbg_kms(connector->dev,
>>>> +				    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>>>> +				    connector->base.id, connector->name,
>>>> +				    info->mso_pixel_overlap);
>>>> +			info->mso_pixel_overlap = 8;
>>>> +		}
>>>>   		drm_dbg_kms(connector->dev,
>>>> -			    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>>>> +			    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>>>   			    connector->base.id, connector->name,
>>>> -			    info->mso_pixel_overlap);
>>>> -		info->mso_pixel_overlap = 8;
>>>> +			    info->mso_stream_count, info->mso_pixel_overlap);
>>>>   	}
>>>> -
>>>> -	drm_dbg_kms(connector->dev,
>>>> -		    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>>> -		    connector->base.id, connector->name,
>>>> -		    info->mso_stream_count, info->mso_pixel_overlap);
>>>>   }
>>>>   
>>>>   static void drm_update_vesa_specific_block(struct drm_connector *connector,
>> 
>

-- 
Jani Nikula, Intel

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Yaroslav]

On 2025-11-26 15:59, Jani Nikula wrote:
> On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
>> On 2025-11-26 15:08, Jani Nikula wrote:
>>> On Wed, 26 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>>>>> Current VESA vendor-specific block parsing expects real block size to be
>>>>> the same as the defined struct size, use real offsets in conditionals
>>>>> instead to add struct fields in future commits.
>>>>>
>>>>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>>>>
>>>> I think this is something we want to backport, since MSO would break
>>>> with bigger vendor-specific blocks, and that leads to black screens on
>>>> MSO displays.
>>>>
>>>> Cc: stable@vger.kernel.org
>>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>>
>>> Oops, I'll take that back.
>>>
>>>>
>>>>> ---
>>>>>    drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
>>>>>    1 file changed, 12 insertions(+), 16 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>>>>> index 64f7a94dd9e4..a52fd6de9327 100644
>>>>> --- a/drivers/gpu/drm/drm_edid.c
>>>>> +++ b/drivers/gpu/drm/drm_edid.c
>>>>> @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>>>    	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>>>>>    		return;
>>>>>    
>>>>> -	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>>>>> +	if (block->num_bytes < 5) {
>>>>>    		drm_dbg_kms(connector->dev,
>>>>>    			    "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
>>>>>    			    connector->base.id, connector->name);
>>>>> @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>>>    		break;
>>>>>    	}
>>>>>    
>>>>> -	if (!info->mso_stream_count) {
>>>>> -		info->mso_pixel_overlap = 0;
>>>
>>> This is no longer cleared for !info->mso_stream_count.
>>>
>>> Perhaps the code could be reorganized to handle it better.
>>
>> It defaults to zero due to drm_reset_display_info()
> 
> Yes, and the code above the context initializes it from the vendor
> block.
> 

It is wrapped in `if (info->mso_stream_count)` so we get

/* From drm_reset_display_info */
info->mso_pixel_overlap = 0;

/* This part was removed, as we don't want the early return here anymore 
due to extended structure length checks
if (!info->mso_stream_count) {
   info->mso_pixel_overlap = 0;
   return;
} */


/* This code is right below your comment */
if (info->mso_stream_count) {
   info->mso_pixel_overlap = ...;
   ...
}

/* I can reinsert the value reset explicitly here, if that's what you 
suggesting to do:

else {
   info->mso_pixel_overlap = 0;
}*/



> 
>>
>>>>> -		return;
>>>>> -	}
>>>>> -
>>>>> -	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>>>> -	if (info->mso_pixel_overlap > 8) {
>>>>> +	if (info->mso_stream_count) {
>>>>> +		info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>>>> +		if (info->mso_pixel_overlap > 8) {
>>>>> +			drm_dbg_kms(connector->dev,
>>>>> +				    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>>>>> +				    connector->base.id, connector->name,
>>>>> +				    info->mso_pixel_overlap);
>>>>> +			info->mso_pixel_overlap = 8;
>>>>> +		}
>>>>>    		drm_dbg_kms(connector->dev,
>>>>> -			    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>>>>> +			    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>>>>    			    connector->base.id, connector->name,
>>>>> -			    info->mso_pixel_overlap);
>>>>> -		info->mso_pixel_overlap = 8;
>>>>> +			    info->mso_stream_count, info->mso_pixel_overlap);
>>>>>    	}
>>>>> -
>>>>> -	drm_dbg_kms(connector->dev,
>>>>> -		    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>>>> -		    connector->base.id, connector->name,
>>>>> -		    info->mso_stream_count, info->mso_pixel_overlap);
>>>>>    }
>>>>>    
>>>>>    static void drm_update_vesa_specific_block(struct drm_connector *connector,
>>>
>>
> 

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Yaroslav]

On 2025-11-26 16:06, Yaroslav wrote:
> 
> 
> On 2025-11-26 15:59, Jani Nikula wrote:
>> On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
>>> On 2025-11-26 15:08, Jani Nikula wrote:
>>>> On Wed, 26 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>>> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>>>>>> Current VESA vendor-specific block parsing expects real block size 
>>>>>> to be
>>>>>> the same as the defined struct size, use real offsets in conditionals
>>>>>> instead to add struct fields in future commits.
>>>>>>
>>>>>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>>>>>
>>>>> I think this is something we want to backport, since MSO would break
>>>>> with bigger vendor-specific blocks, and that leads to black screens on
>>>>> MSO displays.
>>>>>
>>>>> Cc: stable@vger.kernel.org
>>>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>>>
>>>> Oops, I'll take that back.
>>>>
>>>>>
>>>>>> ---
>>>>>>    drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
>>>>>>    1 file changed, 12 insertions(+), 16 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>>>>>> index 64f7a94dd9e4..a52fd6de9327 100644
>>>>>> --- a/drivers/gpu/drm/drm_edid.c
>>>>>> +++ b/drivers/gpu/drm/drm_edid.c
>>>>>> @@ -6544,7 +6544,7 @@ static void 
>>>>>> drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>>>>        if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != 
>>>>>> VESA_IEEE_OUI)
>>>>>>            return;
>>>>>> -    if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>>>>>> +    if (block->num_bytes < 5) {
>>>>>>            drm_dbg_kms(connector->dev,
>>>>>>                    "[CONNECTOR:%d:%s] Unexpected VESA vendor block 
>>>>>> size\n",
>>>>>>                    connector->base.id, connector->name);
>>>>>> @@ -6567,24 +6567,20 @@ static void 
>>>>>> drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>>>>            break;
>>>>>>        }
>>>>>> -    if (!info->mso_stream_count) {
>>>>>> -        info->mso_pixel_overlap = 0;
>>>>
>>>> This is no longer cleared for !info->mso_stream_count.
>>>>
>>>> Perhaps the code could be reorganized to handle it better.
>>>
>>> It defaults to zero due to drm_reset_display_info()
>>
>> Yes, and the code above the context initializes it from the vendor
>> block.
>>
> 
> It is wrapped in `if (info->mso_stream_count)` so we get
> 
> /* From drm_reset_display_info */
> info->mso_pixel_overlap = 0;
> 
> /* This part was removed, as we don't want the early return here anymore 
> due to extended structure length checks
> if (!info->mso_stream_count) {
>    info->mso_pixel_overlap = 0;
>    return;
> } */
> 
> 
> /* This code is right below your comment */
> if (info->mso_stream_count) {
>    info->mso_pixel_overlap = ...;
>    ...
> }
> 
> /* I can reinsert the value reset explicitly here, if that's what you 
> suggesting to do:
> 
> else {
>    info->mso_pixel_overlap = 0;
> }*/
> 
> 

For reference, repository state at the point after this patch:

https://github.com/CertainLach/linux-1/blob/01b0097171ebe85ae124a7b535dce0b46a1dd8e2/drivers/gpu/drm/drm_edid.c#L6561-L6593

Commit: 
https://github.com/CertainLach/linux-1/commit/01b0097171ebe85ae124a7b535dce0b46a1dd8e2

(Note that the fix for DP/EDP mistake is already here, but nothing else 
was changed in the github version of this patch)

> 
>>
>>>
>>>>>> -        return;
>>>>>> -    }
>>>>>> -
>>>>>> -    info->mso_pixel_overlap = 
>>>>>> FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>>>>> -    if (info->mso_pixel_overlap > 8) {
>>>>>> +    if (info->mso_stream_count) {
>>>>>> +        info->mso_pixel_overlap = 
>>>>>> FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>>>>> +        if (info->mso_pixel_overlap > 8) {
>>>>>> +            drm_dbg_kms(connector->dev,
>>>>>> +                    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap 
>>>>>> value %u\n",
>>>>>> +                    connector->base.id, connector->name,
>>>>>> +                    info->mso_pixel_overlap);
>>>>>> +            info->mso_pixel_overlap = 8;
>>>>>> +        }
>>>>>>            drm_dbg_kms(connector->dev,
>>>>>> -                "[CONNECTOR:%d:%s] Reserved MSO pixel overlap 
>>>>>> value %u\n",
>>>>>> +                "[CONNECTOR:%d:%s] MSO stream count %u, pixel 
>>>>>> overlap %u\n",
>>>>>>                    connector->base.id, connector->name,
>>>>>> -                info->mso_pixel_overlap);
>>>>>> -        info->mso_pixel_overlap = 8;
>>>>>> +                info->mso_stream_count, info->mso_pixel_overlap);
>>>>>>        }
>>>>>> -
>>>>>> -    drm_dbg_kms(connector->dev,
>>>>>> -            "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap 
>>>>>> %u\n",
>>>>>> -            connector->base.id, connector->name,
>>>>>> -            info->mso_stream_count, info->mso_pixel_overlap);
>>>>>>    }
>>>>>>    static void drm_update_vesa_specific_block(struct drm_connector 
>>>>>> *connector,
>>>>
>>>
>>

Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension

[Jani Nikula]

On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
> On 2025-11-26 16:06, Yaroslav wrote:
>> 
>> 
>> On 2025-11-26 15:59, Jani Nikula wrote:
>>> On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
>>>> On 2025-11-26 15:08, Jani Nikula wrote:
>>>>> On Wed, 26 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>>>> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>>>>>>> Current VESA vendor-specific block parsing expects real block size 
>>>>>>> to be
>>>>>>> the same as the defined struct size, use real offsets in conditionals
>>>>>>> instead to add struct fields in future commits.
>>>>>>>
>>>>>>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>>>>>>
>>>>>> I think this is something we want to backport, since MSO would break
>>>>>> with bigger vendor-specific blocks, and that leads to black screens on
>>>>>> MSO displays.
>>>>>>
>>>>>> Cc: stable@vger.kernel.org
>>>>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>>>>
>>>>> Oops, I'll take that back.

Yeah, my bad, I'll take back me taking that back. Original Reviewed-by
stands. Sorry for the noise.

BR,
Jani.


-- 
Jani Nikula, Intel