From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43C0CC43603 for ; Tue, 17 Dec 2019 02:04:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 119D22053B for ; Tue, 17 Dec 2019 02:04:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726696AbfLQCEg (ORCPT ); Mon, 16 Dec 2019 21:04:36 -0500 Received: from mga07.intel.com ([134.134.136.100]:26146 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726133AbfLQCEf (ORCPT ); Mon, 16 Dec 2019 21:04:35 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Dec 2019 18:04:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,323,1571727600"; d="scan'208";a="227326453" Received: from allen-box.sh.intel.com (HELO [10.239.159.136]) ([10.239.159.136]) by orsmga002.jf.intel.com with ESMTP; 16 Dec 2019 18:04:32 -0800 Cc: baolu.lu@linux.intel.com, "Raj, Ashok" , "Kumar, Sanjay K" , "jacob.jun.pan@linux.intel.com" , "Tian, Kevin" , "Sun, Yi Y" , Peter Xu , "iommu@lists.linux-foundation.org" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first level To: "Liu, Yi L" , Joerg Roedel , David Woodhouse , Alex Williamson References: <20191211021219.8997-1-baolu.lu@linux.intel.com> <20191211021219.8997-5-baolu.lu@linux.intel.com> From: Lu Baolu Message-ID: Date: Tue, 17 Dec 2019 10:03:41 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Yi, On 12/15/19 5:37 PM, Liu, Yi L wrote: >> XD (bit 63) is only for the first level, and SNP (bit 11) is only for second level, right? I >> think we need to always set XD bit for IOVA over FL case. thoughts? > Oops, I made a mistake here. Please forget SNP bit, there is no way to control SNP > with first level page table.:-) > > Actually, it is execute (bit 1) of second level page table which I wanted to say. > If software sets R/W/X permission to an IOVA, with IOVA over second level > page table, it will set bit 1. However, if IOVA is over first level page table, it > may need to clear XD bit. This is what I want to say here. If IOVA doesn’t allow > execute permission, it's ok to always set XD bit for IOVA over FL case. But I > would like to do it just as what we did for R/W permission. R/W permission > relies on the permission configured by the page map caller. right? Got your point. Current driver always cleard X (bit 2) in the second level page table. So we will always set XD bit (bit 63) in the first level page table. If we decide to use the X permission, we need a separated patch, right? Best regards, baolu