Re: [PATCH v2] clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set

[barnabas.czeman@mainlining.org]

On 2024-09-25 23:28, Dmitry Baryshkov wrote:
> On Wed, Sep 25, 2024 at 08:33:20PM GMT, Barnabás Czémán wrote:
>> Many qcom clock drivers do not have .width set. In that case value of
>> (p)->width - 1 will be negative which breaks clock tree. Fix this
>> by checking if width is zero, and pass 3 to GENMASK if that's the 
>> case.
>> 
>> Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
>> Fixes: 2c4553e6c485 ("clk: qcom: clk-alpha-pll: Fix the pll post div 
>> mask")
> 
> I think one Fixes tag should be enough.
Should I send a v3 remove one of them or not needed?
> 
> Nevertheless,
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
>> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
>> ---
>> Changes in v2:
>> - Pass 3 to GENMASK instead of 0.
>> - Add more Fixes tag for reference root cause.
>> - Link to v1: 
>> https://lore.kernel.org/r/20240925-fix-postdiv-mask-v1-1-f70ba55f415e@mainlining.org
>> ---
>>  drivers/clk/qcom/clk-alpha-pll.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)