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[91.79.162.197]) by smtp.googlemail.com with ESMTPSA id v7sm2272996ljj.3.2019.06.10.17.01.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Jun 2019 17:01:33 -0700 (PDT) Subject: Re: [PATCH v3 0/8] memory: tegra: Introduce Tegra30 EMC driver From: Dmitry Osipenko To: Peter De Schrijver , Stephen Boyd Cc: Rob Herring , Michael Turquette , Joseph Lo , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190524172353.29087-1-digetx@gmail.com> Message-ID: Date: Tue, 11 Jun 2019 03:01:31 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190524172353.29087-1-digetx@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 24.05.2019 20:23, Dmitry Osipenko пишет: > Hello, > > This series introduces driver for the External Memory Controller (EMC) > found on Tegra30 chips, it controls the external DRAM on the board. The > purpose of this driver is to program memory timing for external memory on > the EMC clock rate change. The driver was tested using the ACTMON devfreq > driver that performs memory frequency scaling based on memory-usage load. > > Changelog: > > v3: - Addressed review comments that were made by Stephen Boyd to v2 by > adding explicit typing for the callback variable, by including > "clk-provider.h" directly in the code and by dropping __clk_lookup > usage where possible. > > Added more patches into this series: > > memory: tegra20-emc: Drop setting EMC rate to max on probe > memory: tegra20-emc: Adapt for clock driver changes > memory: tegra20-emc: Include io.h instead of iopoll.h > memory: tegra20-emc: Replace clk_get_sys with devm_clk_get > > Initially I was going to include these patches into other patchset, > but changed my mind after rearranging things a tad. The "Adapt for > clock driver changes" patch is directly related to the clock changes > done in the first patch of this series, the rest are minor cleanups > that are fine to include here as well. > > Added some more words to the commit message of "Add binding for NVIDIA > Tegra30 External Memory Controller" patch, clarifying why common DDR > timing device-tree form isn't suitable for Tegra30. > > The Tegra30 EMC driver now explicitly selects the registers access > mode (EMC_DBG mux), not relying on the setting left from bootloader. > > v2: - Added support for changing MC clock diver configuration based on > Memory Controller (MC) configuration which is part of the memory > timing. > > - Merged the "Add custom EMC clock implementation" patch into this > series because the "Introduce Tegra30 EMC driver" patch directly > depends on it. Please note that Tegra20 EMC driver will need to be > adapted for the clock changes as well, I'll send out the Tegra20 > patches after this series will be applied because of some other > dependencies (devfreq) and because the temporary breakage won't > be critical (driver will just error out on probe). > > - EMC driver now performs MC configuration validation by checking > that the number of MC / EMC timings matches and that the timings > rate is the same. > > - EMC driver now supports timings that want to change the MC clock > configuration. > > - Other minor prettifying changes of the code. > > Dmitry Osipenko (8): > clk: tegra20/30: Add custom EMC clock implementation > memory: tegra20-emc: Drop setting EMC rate to max on probe > memory: tegra20-emc: Adapt for clock driver changes > memory: tegra20-emc: Include io.h instead of iopoll.h > memory: tegra20-emc: Replace clk_get_sys with devm_clk_get > dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory > Controller > memory: tegra: Introduce Tegra30 EMC driver > ARM: dts: tegra30: Add External Memory Controller node > > .../memory-controllers/nvidia,tegra30-emc.txt | 249 ++++ > arch/arm/boot/dts/tegra30.dtsi | 11 + > drivers/clk/tegra/Makefile | 2 + > drivers/clk/tegra/clk-tegra20-emc.c | 299 +++++ > drivers/clk/tegra/clk-tegra20.c | 55 +- > drivers/clk/tegra/clk-tegra30.c | 38 +- > drivers/clk/tegra/clk.h | 6 + > drivers/memory/tegra/Kconfig | 10 + > drivers/memory/tegra/Makefile | 1 + > drivers/memory/tegra/mc.c | 3 - > drivers/memory/tegra/mc.h | 30 +- > drivers/memory/tegra/tegra20-emc.c | 94 +- > drivers/memory/tegra/tegra30-emc.c | 1165 +++++++++++++++++ > drivers/memory/tegra/tegra30.c | 44 + > include/linux/clk/tegra.h | 14 + > 15 files changed, 1903 insertions(+), 118 deletions(-) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.txt > create mode 100644 drivers/clk/tegra/clk-tegra20-emc.c > create mode 100644 drivers/memory/tegra/tegra30-emc.c > Hello Peter, Do you have any comments on the clk/emc bits? It looks to me that this series basically needs yours, Stephen's and Rob's acks, after which Thierry could pick it up once everything is arranged. Stephen and Rob already made some comments to the previous versions of the series that hopefully are addressed now. Maybe you also have something to say? Otherwise just an ack will be also very appreciated. Thanks in advance! Actually just noticed that I accidentally missed to CC Stephen directly for this series, but hopefully it's not a problem since he is reading the CLK ML. Stephen, please let me know otherwise, I could re-send it all if needed.