[PATCH V2 0/2] Enable Inline crypto engine for QCS8300

[PATCH V2 0/2] Enable Inline crypto engine for QCS8300

[Yuvaraj Ranganathan]

Document and add device-tree node to enable Inline crypto engine for QCS8300

This series depends on below patch series:
https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com/ - Reviewed

Changes in v2:
 - extend UFS ICE to the full register range
 - Link to v1: https://lore.kernel.org/all/20241113043351.2889027-1-quic_yrangana@quicinc.com/

Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
---
Yuvaraj Ranganathan (2):
  dt-bindings: crypto: ice: document the qcs8300 inline crypto engine
  arm64: dts: qcom: qcs8300: enable the inline crypto engine

 .../bindings/crypto/qcom,inline-crypto-engine.yaml        | 1 +
 arch/arm64/boot/dts/qcom/qcs8300.dtsi                     | 8 ++++++++
 2 files changed, 9 insertions(+)

-- 
2.34.1

[PATCH V2 1/2] dt-bindings: crypto: ice: document the qcs8300 inline crypto engine

[Yuvaraj Ranganathan]

Add the compatible string for QCom ICE on qcs8300 SoCs.

Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
---
 .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 0304f074cf08..657693867ddf 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs8300-inline-crypto-engine
           - qcom,sa8775p-inline-crypto-engine
           - qcom,sc7180-inline-crypto-engine
           - qcom,sc7280-inline-crypto-engine
-- 
2.34.1

[PATCH V2 2/2] arm64: dts: qcom: qcs8300: enable the inline crypto engine

[Yuvaraj Ranganathan]

Add an ICE node to qcs8300 SoC description and enable it by adding a
phandle to the UFS node.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 2c35f96c3f28..ab91c3b7bba6 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -685,6 +685,7 @@ &mc_virt SLAVE_EBI1 0>,
 					<0 0>,
 					<0 0>,
 					<0 0>;
+			qcom,ice = <&ice>;
 			status = "disabled";
 		};
 
@@ -710,6 +711,13 @@ ufs_mem_phy: phy@1d87000 {
 			status = "disabled";
 		};
 
+		ice: crypto@1d88000 {
+			compatible = "qcom,qcs8300-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x01d88000 0x0 0x18000>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x0 0x01f40000 0x0 0x20000>;
-- 
2.34.1

Re: [PATCH V2 2/2] arm64: dts: qcom: qcs8300: enable the inline crypto engine

[Konrad Dybcio]

On 22.11.2024 2:20 PM, Yuvaraj Ranganathan wrote:
> Add an ICE node to qcs8300 SoC description and enable it by adding a
> phandle to the UFS node.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Getting *a review* does *not* mean I gave you a Reviewed-by tag.

https://docs.kernel.org/process/submitting-patches.html#using-reported-by-tested-by-reviewed-by-suggested-by-and-fixes

> Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 2c35f96c3f28..ab91c3b7bba6 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -685,6 +685,7 @@ &mc_virt SLAVE_EBI1 0>,
>  					<0 0>,
>  					<0 0>,
>  					<0 0>;
> +			qcom,ice = <&ice>;
>  			status = "disabled";
>  		};
>  
> @@ -710,6 +711,13 @@ ufs_mem_phy: phy@1d87000 {
>  			status = "disabled";
>  		};
>  
> +		ice: crypto@1d88000 {
> +			compatible = "qcom,qcs8300-inline-crypto-engine",
> +				     "qcom,inline-crypto-engine";
> +			reg = <0x0 0x01d88000 0x0 0x18000>;
> +			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> +		};

Although this looks good now, so I'll allow you to keep it.

I won't add it a second time here to avoid confusing the maintainer
tools.

Konrad

Re: [PATCH V2 2/2] arm64: dts: qcom: qcs8300: enable the inline crypto engine

[Krzysztof Kozlowski]

On 22/11/2024 14:20, Yuvaraj Ranganathan wrote:
> Add an ICE node to qcs8300 SoC description and enable it by adding a
> phandle to the UFS node.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

This did not happen. Provide a proof (lore link).

Best regards,
Krzysztof

Re: [PATCH V2 2/2] arm64: dts: qcom: qcs8300: enable the inline crypto engine

[Yuvaraj Ranganathan]

Hi Krzysztof,

Same mistake is done for this patch series as well.

I sincerely apologize for the inconvenience. I will remove the tag
in the next patch series.

Thanks,
Yuvaraj.


On 11/22/2024 8:25 PM, Krzysztof Kozlowski wrote:
> On 22/11/2024 14:20, Yuvaraj Ranganathan wrote:
>> Add an ICE node to qcs8300 SoC description and enable it by adding a
>> phandle to the UFS node.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> This did not happen. Provide a proof (lore link).
> 
> Best regards,
> Krzysztof