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([2a10:bac0:b000:7579:7285:c2ff:fedd:7e3a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4247d0c54d9sm217268865e9.28.2024.06.25.06.19.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Jun 2024 06:19:41 -0700 (PDT) Message-ID: Date: Tue, 25 Jun 2024 16:19:40 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/5] x86/mce: Define mce_prep_record() helpers for common and per-CPU fields To: Yazen Ghannam , linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tony.luck@intel.com, x86@kernel.org, avadhut.naik@amd.com, john.allen@amd.com References: <20240624212008.663832-1-yazen.ghannam@amd.com> <20240624212008.663832-5-yazen.ghannam@amd.com> From: Nikolay Borisov Content-Language: en-US In-Reply-To: <20240624212008.663832-5-yazen.ghannam@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 25.06.24 г. 0:20 ч., Yazen Ghannam wrote: > Generally, MCA information for an error is gathered on the CPU that > reported the error. In this case, CPU-specific information from the > running CPU will be correct. > > However, this will be incorrect if the MCA information is gathered while > running on a CPU that didn't report the error. One example is creating > an MCA record using mce_prep_record() for errors reported from ACPI. > > Split mce_prep_record() so that there is a helper function to gather > common, i.e. not CPU-specific, information and another helper for > CPU-specific information. > > Leave mce_prep_record() defined as-is for the common case when running > on the reporting CPU. > > Get MCG_CAP in the global helper even though the register is per-CPU. > This value is not already cached per-CPU like other values. And it does > not assist with any per-CPU decoding or handling. > > Signed-off-by: Yazen Ghannam > --- > Link: > https://lkml.kernel.org/r/20240521125434.1555845-3-yazen.ghannam@amd.com > > v1->v2: > * No change. > > arch/x86/kernel/cpu/mce/core.c | 34 ++++++++++++++++++++---------- > arch/x86/kernel/cpu/mce/internal.h | 2 ++ > 2 files changed, 25 insertions(+), 11 deletions(-) > > diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c > index dd5192ef52e0..0133f88dfffb 100644 > --- a/arch/x86/kernel/cpu/mce/core.c > +++ b/arch/x86/kernel/cpu/mce/core.c > @@ -117,20 +117,32 @@ static struct irq_work mce_irq_work; > */ > BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); > > -/* Do initial initialization of a struct mce */ > -void mce_prep_record(struct mce *m) > +void mce_prep_record_common(struct mce *m) > { > memset(m, 0, sizeof(struct mce)); > - m->cpu = m->extcpu = smp_processor_id(); > + > + m->cpuid = cpuid_eax(1); > + m->cpuvendor = boot_cpu_data.x86_vendor; > + m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); > /* need the internal __ version to avoid deadlocks */ > - m->time = __ktime_get_real_seconds(); > - m->cpuvendor = boot_cpu_data.x86_vendor; > - m->cpuid = cpuid_eax(1); > - m->socketid = cpu_data(m->extcpu).topo.pkg_id; > - m->apicid = cpu_data(m->extcpu).topo.initial_apicid; > - m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); > - m->ppin = cpu_data(m->extcpu).ppin; > - m->microcode = boot_cpu_data.microcode; > + m->time = __ktime_get_real_seconds(); > +} > + > +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m) > +{ > + m->cpu = cpu; > + m->extcpu = cpu; > + m->apicid = cpu_data(m->extcpu).topo.initial_apicid; > + m->microcode = cpu_data(m->extcpu).microcode; > + m->ppin = cpu_data(m->extcpu).ppin; nit: Similar to tglx's feedback for patch 2 you could use topology_ppin() > + m->socketid = cpu_data(m->extcpu).topo.pkg_id; nit: topology_physical_package_id() > +} > +