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([2001:b07:6468:f312:e56d:fbdf:8b79:c79c]) by smtp.gmail.com with ESMTPSA id r20sm9288291wrg.61.2019.10.04.00.22.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Oct 2019 00:22:42 -0700 (PDT) Subject: Re: [RFC PATCH 00/13] XOM for KVM guest userspace To: Rick Edgecombe , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, linux-mm@kvack.org, luto@kernel.org, peterz@infradead.org, dave.hansen@intel.com, sean.j.christopherson@intel.com, keescook@chromium.org Cc: kristen@linux.intel.com, deneen.t.dock@intel.com References: <20191003212400.31130-1-rick.p.edgecombe@intel.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: Date: Fri, 4 Oct 2019 09:22:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20191003212400.31130-1-rick.p.edgecombe@intel.com> Content-Language: en-US X-MC-Unique: BNVYoja6Mj-SFHpO4z-qPA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/10/19 23:23, Rick Edgecombe wrote: > Since software would have previously received a #PF with the RSVD error c= ode > set, when the HW encountered any set bits in the region 51 to M, there wa= s some > internal discussion on whether this should have a virtual MSR for the OS = to turn > it on only if the OS knows it isn't relying on this behavior for bit M. T= he > argument against needing an MSR is this blurb from the Intel SDM about re= served > bits: > "Bits reserved in the paging-structure entries are reserved for future > functionality. Software developers should be aware that such bits may be = used in > the future and that a paging-structure entry that causes a page-fault exc= eption > on one processor might not do so in the future." >=20 > So in the current patchset there is no MSR write required for the guest t= o turn > on this feature. It will have this behavior whenever qemu is run with > "-cpu +xo". I think the part of the manual that you quote is out of date. Whenever Intel has "unreserved" bits in the page tables they have done that only if specific bits in CR4 or EFER or VMCS execution controls are set; this is a good thing, and I'd really like it to be codified in the SDM. The only bits for which this does not (and should not) apply are indeed bits 51:MAXPHYADDR. But the SDM makes it clear that bits 51:MAXPHYADDR are reserved, hence "unreserving" bits based on just a QEMU command line option would be against the specification. So, please don't do this and introduce an MSR that enables the feature. Paolo