Re: [PATCH 4/5] arm64: dts: ti: Introduce base support for AM62x SoC

Krzysztof Kozlowski
2022-02-08T17:05:59Z

On 08/02/2022 14:18, Vignesh Raghavendra wrote:
> The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
> architecture platform, providing ultra-low-power modes, dual display,
> multi-sensor edge compute, security and other BOM-saving integration.
> The AM62 SoC targets broad market to enable applications such as
> Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
> Automation, Appliances and more.
>
> Some highlights of this SoC are:
>
> * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
> Pin-to-pin compatible options for single and quad core are available.
> * Cortex-M4F for general-purpose or safety usage.
> * Dual display support, providing 24-bit RBG parallel interface and
> OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
> resolution.
> * Selectable GPUsupport, up to 8GFLOPS, providing better user experience
> in 3D graphic display case and Android.
> * PRU(Programmable Realtime Unit) support for customized programmable
> interfaces/IOs.
> * Integrated Giga-bit Ethernet switch supporting up to a total of two
> external ports (TSN capable).
> * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
> NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
> 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
> * Dedicated Centralized System Controller for Security, Power, and
> Resource Management.
> * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
> enabling battery powered system design.
>
> This add bare minimum DT describing ARM compute clusters, Main, MCU and
> Wakeup domain and interconnects, UARTs and I2Cs to enable booting using
> ramdisk.
>
> More details can be found in the Technical Reference Manual:
> https://www.ti.com/lit/pdf/spruiv7
>
> Co-developed-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Co-developed-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 263 +++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 36 +++
> arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 41 ++++
> arch/arm64/boot/dts/ti/k3-am62.dtsi | 104 ++++++++
> arch/arm64/boot/dts/ti/k3-am625.dtsi | 103 ++++++++
> 5 files changed, 547 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am625.dtsi
>

(...)

> diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi
> new file mode 100644
> index 000000000000..f1a46be27c37
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi
> @@ -0,0 +1,104 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for AM62 SoC Family
> + *
> + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/k3.h>
> +#include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> +/ {
> + model = "Texas Instruments K3 AM625 SoC";
> + compatible = "ti,am625";

This is am625, but the file is am62. Why having the split?

> + interrupt-parent = <&gic500>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> +
> + psci: psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> + };
> +
> + a53_timer0: timer-cl0-cpu0 {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
> + };
> +
> + pmu: pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + cbass_main: bus@f0000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
> + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
> + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
> + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
> + <0x00 0x0070C000 0x00 0x0070C000 0x00 0x00000200>, /* USB1 debug trace */
> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
> + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
> + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
> + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
> + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
> + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
> + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
> + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
> + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
> + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* sa3 sproxy data */
> + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
> + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* sa3 sproxy config */
> + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
> + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
> + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
> + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
> + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
> +
> + /* MCU Domain Range */
> + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
> +
> + /* Wakeup Domain Range */
> + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
> + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
> +
> + cbass_mcu: bus@4000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
> + };
> +
> + cbass_wakeup: bus@2b000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
> + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
> + };
> + };
> +};
> +
> +/* Now include the peripherals for each bus segments */
> +#include "k3-am62-main.dtsi"
> +#include "k3-am62-mcu.dtsi"
> +#include "k3-am62-wakeup.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi
> new file mode 100644
> index 000000000000..887f31c23fef
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for AM625 SoC family in Quad core configuration
> + *
> + * TRM: https://www.ti.com/lit/pdf/spruiv7
> + *
> + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-am62.dtsi"
> +
> +/ {
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +

This file is not included anywhere, so does it mean that your SoC comes
without the cores and each board designer plugs the cores separately?

Best regards,
Krzysztof