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Thu, 27 Mar 2025 23:52:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEHcHQwhgg0IH/oYdx4ttXb7q2lYkNiP8atH6NOJ54/TnmCTiuOM9YtfoaujKYd6jAJA9jQZA== X-Received: by 2002:a05:6a00:88e:b0:736:5545:5b84 with SMTP id d2e1a72fcca58-73960e0cdb6mr11297875b3a.3.1743144750186; Thu, 27 Mar 2025 23:52:30 -0700 (PDT) Received: from [10.92.192.202] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-739710b493esm1016147b3a.149.2025.03.27.23.52.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Mar 2025 23:52:29 -0700 (PDT) Message-ID: Date: Fri, 28 Mar 2025 12:22:23 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v8 2/4] PCI: of: Add of_pci_get_equalization_presets() API Content-Language: en-US To: Manivannan Sadhasivam Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com References: <20250316-preset_v6-v8-0-0703a78cb355@oss.qualcomm.com> <20250316-preset_v6-v8-2-0703a78cb355@oss.qualcomm.com> <7a0724ad-89a5-0ccd-eba5-ca4871ce1cdd@oss.qualcomm.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Ha4bSWMifSA8IX8Nb8lTDUNp7LDB5Fx5 X-Proofpoint-GUID: Ha4bSWMifSA8IX8Nb8lTDUNp7LDB5Fx5 X-Authority-Analysis: v=2.4 cv=Q43S452a c=1 sm=1 tr=0 ts=67e64730 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=gJnbMjkyvPzYppnzV1QA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-28_03,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 suspectscore=0 adultscore=0 mlxlogscore=995 malwarescore=0 mlxscore=0 priorityscore=1501 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503280045 On 3/28/2025 12:13 PM, Manivannan Sadhasivam wrote: > On Fri, Mar 28, 2025 at 10:54:25AM +0530, Krishna Chaitanya Chundru wrote: >> >> >> On 3/28/2025 10:09 AM, Manivannan Sadhasivam wrote: >>> On Sun, Mar 16, 2025 at 09:39:02AM +0530, Krishna Chaitanya Chundru wrote: >>>> PCIe equalization presets are predefined settings used to optimize >>>> signal integrity by compensating for signal loss and distortion in >>>> high-speed data transmission. >>>> >>>> As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates >>>> of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to >>>> configure lane equalization presets for each lane to enhance the PCIe >>>> link reliability. Each preset value represents a different combination >>>> of pre-shoot and de-emphasis values. For each data rate, different >>>> registers are defined: for 8.0 GT/s, registers are defined in section >>>> 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has >>>> an extra receiver preset hint, requiring 16 bits per lane, while the >>>> remaining data rates use 8 bits per lane. >>>> >>>> Based on the number of lanes and the supported data rate, >>>> of_pci_get_equalization_presets() reads the device tree property and >>>> stores in the presets structure. >>>> >>>> Signed-off-by: Krishna Chaitanya Chundru >>>> --- >>>> drivers/pci/of.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ >>>> drivers/pci/pci.h | 32 +++++++++++++++++++++++++++++++- >>>> 2 files changed, 75 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/pci/of.c b/drivers/pci/of.c >>>> index 7a806f5c0d20..18691483e108 100644 >>>> --- a/drivers/pci/of.c >>>> +++ b/drivers/pci/of.c >>>> @@ -851,3 +851,47 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, >>>> return slot_power_limit_mw; >>>> } >>>> EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); >>>> + >>>> +/** >>>> + * of_pci_get_equalization_presets - Parses the "eq-presets-Ngts" property. >>>> + * >>>> + * @dev: Device containing the properties. >>>> + * @presets: Pointer to store the parsed data. >>>> + * @num_lanes: Maximum number of lanes supported. >>>> + * >>>> + * If the property is present, read and store the data in the @presets structure. >>>> + * Else, assign a default value of PCI_EQ_RESV. >>>> + * >>>> + * Return: 0 if the property is not available or successfully parsed else >>>> + * errno otherwise. >>>> + */ >>>> +int of_pci_get_equalization_presets(struct device *dev, >>>> + struct pci_eq_presets *presets, >>>> + int num_lanes) >>>> +{ >>>> + char name[20]; >>>> + int ret; >>>> + >>>> + presets->eq_presets_8gts[0] = PCI_EQ_RESV; >>>> + ret = of_property_read_u16_array(dev->of_node, "eq-presets-8gts", >>>> + presets->eq_presets_8gts, num_lanes); >>>> + if (ret && ret != -EINVAL) { >>>> + dev_err(dev, "Error reading eq-presets-8gts :%d\n", ret); >>> >>> 'Error reading eq-presets-8gts: %d' >>> >>>> + return ret; >>>> + } >>>> + >>>> + for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) { >>>> + presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; >>>> + snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << (i + 1)); >>>> + ret = of_property_read_u8_array(dev->of_node, name, >>>> + presets->eq_presets_Ngts[i], >>>> + num_lanes); >>>> + if (ret && ret != -EINVAL) { >>>> + dev_err(dev, "Error reading %s :%d\n", name, ret); >>> >>> 'Error reading %s: %d' >>> >>>> + return ret; >>>> + } >>>> + } >>>> + >>>> + return 0; >>>> +} >>>> +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); >>>> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h >>>> index 01e51db8d285..78c9cc0ad8fa 100644 >>>> --- a/drivers/pci/pci.h >>>> +++ b/drivers/pci/pci.h >>>> @@ -9,6 +9,8 @@ struct pcie_tlp_log; >>>> /* Number of possible devfns: 0.0 to 1f.7 inclusive */ >>>> #define MAX_NR_DEVFNS 256 >>>> +#define MAX_NR_LANES 16 >>> >>> Why did you limit to 16? >>> >> As per PCIe spec we support maximum of 16 lanes only right >> > > No. PCIe spec defines Max Link Width up to 32 lanes. Though, we have only seen > 16 lanes used widely. This field should correspond to 'Maximum Link Width' value > in the Link Capabilities Register. > As per spec 6.0.1 section 7.5.3.6 Link Capabilities Register max link width is x16 only. - Krishna Chaitanya. > - Mani >