Re: AMD MP, SMP, Tyan 2466

Herbert Poetzl
2003-06-26T14:58:29Z

On Thu, Jun 26, 2003 at 12:40:41AM +0100, Edward Tandi wrote:
> On Thu, 2003-06-26 at 00:26, Timothy Miller wrote:
> > Edward Tandi wrote:
> > > On Wed, 2003-06-25 at 23:59, Timothy Miller wrote:
> > >>
> > >>DDR memory works very much like single data rate, except that data is
> > >>transferred (in whichever direction it's going) on both edges of the
> > >>clock, thus doubling the transfer rate. The memory does not switch
> > >>between reading and writing as you describe it.
> > >>
> > >>I believe registering is for reliability. Data is transferred one clock
> > >>cycle later but reduces signal loading.
> > >
> > >
> > > Thanks for the clarification. I do not profess to be an expert in the
> > > technology. Two writes or a read+write per clock cycle is close enough
> > > for the purpose of the discussion.
> > >
> > > The point I was trying to make is that the registers are there to deal
> > > with an SMP race condition of some sort. Athlon MP motherboards fitted
> > > with two processors will not work properly without 'registered' RAM. I
> > > have hard experience of this and it this experience I am sharing with
> > > someone who is seeing the same symptoms.
> >
> >
> > It is my understanding that the registered memory requirement has
> > nothing to do with SMP but instead with the amount of memory you have.
>
> Except if you go to the beginning of this thread, you will see that the
> machine appears to be running fine in Uniprocessor mode. This concurs
> with my experience. The only difference is that Artur switched the
> kernel whereas I pulled a CPU (and kept the SMP kernel).
>
> > The more memory chips you have, the greater the signal loading on the
> > memory bus. More input drivers means more capacitance which means you
> > need your output drivers to put out data sooner (relative to the clock
> > edge, so registered delays by one clock) and stronger (greater drive
> > strength).

hmm, AFAIK, registered memory has an additional chip/device
called a 'register' (a latch), which buffers/synchronizes the
data going in and out. this processes, as mentioned, requires
an additional clock cycle, but in turn improves signal strength
and stability (by re-driving control/data signals) ...

> I only have 2 x 256MB in the box.
>
> > In an SMP system (besides NUMA), multiple processors will talk to the
> > same memory through a shared memory controller (like in a Northbridge),
> > so although there are multiple processors, there is still only one
> > memory bus. Pulling off one CPU isn't going to change that situation.
>
> It appears to do the trick in practise though. How strange.

SMP systems do much more MIO (non sequential memory access)
than UP systems ... so any issues regarding correctness of
the signalling, will be amplified ...

HTH,
Herbert

> Ed-T.
>
>
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