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Tue, 22 Aug 2023 11:47:05 GMT Received: from [10.216.34.168] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 22 Aug 2023 04:47:00 -0700 Message-ID: Date: Tue, 22 Aug 2023 17:16:57 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH 4/4] arm64: dts: qcom: qdu1000: Add ECPRI clock controller Content-Language: en-US To: Konrad Dybcio , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson CC: Taniya Das , , , , , Ajit Pandey , Jagadeesh Kona References: <20230808051407.647395-1-quic_imrashai@quicinc.com> <20230808051407.647395-5-quic_imrashai@quicinc.com> <28452f19-be57-46db-bfc8-4ba8573de1d0@linaro.org> From: Imran Shaik In-Reply-To: <28452f19-be57-46db-bfc8-4ba8573de1d0@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: c_OlHcvxv7Mbfwfyc09OnYbLCqAL-lWZ X-Proofpoint-GUID: c_OlHcvxv7Mbfwfyc09OnYbLCqAL-lWZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-22_10,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 mlxlogscore=869 suspectscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308220089 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/10/2023 1:30 AM, Konrad Dybcio wrote: > On 8.08.2023 07:14, Imran Shaik wrote: >> Add device node for ECPRI clock controller on qcom QDU1000 >> and QRU1000 SoCs. >> >> Signed-off-by: Imran Shaik >> --- >> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> index 1c0e5d271e91..63930f944b65 100644 >> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> @@ -381,6 +381,20 @@ gcc: clock-controller@80000 { >> #power-domain-cells = <1>; >> }; >> >> + ecpricc: clock-controller@280000 { >> + compatible = "qcom,qdu1000-ecpricc"; >> + reg = <0x0 0x00280000 0x0 0x31c00>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; > Please align the entries with the first < (probably missing a single > space in the front) > > Konrad Sure, will update and push next series. Thanks, Imran