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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-61cfc1c77d0sm13953740a12.11.2025.09.04.01.36.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 01:36:38 -0700 (PDT) Message-ID: Date: Thu, 4 Sep 2025 10:36:35 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V5 4/4] arm64: dts: qcom: sm8550: Add max-sd-hs-hz property To: Krzysztof Kozlowski , Sarthak Garg , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20250903080404.3260135-1-quic_sartgarg@quicinc.com> <20250903080404.3260135-5-quic_sartgarg@quicinc.com> <6deac56f-e21a-4447-bfa7-a414084676b8@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <6deac56f-e21a-4447-bfa7-a414084676b8@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAxOSBTYWx0ZWRfXz+4Da+jycORP 5ucc/9Y+yabId9gDLCfJxE0xQ1haqK7aoCand2nfbWTTKqowV4CFODoNF/VNnLTMtag5evDE8pp rF7W9H3zWUhWo41K3iMbZur4wt+QByqxeTPJRewut5NMFee2H0bWrIm0XvuWN46cHv6U4BnNMiT SR+2HCjVKO7iBv+tSpFiXN5RisEsqNyXkcqnctuCYule8PiZoVLepTFeTVShn6UBWg+JjllxxUQ ZuR5s3ZDZW2yAx88MGKrVFmUYun+n5VBSsUTROPxkDMjN52ZXt0oxW98iejyzDcICRoj22MqMKz x+RMJRXXH3eIn+WC3tcYpY2ifWUCxtOq6p7A0BumwX5n+jOKWp6+9r3ZCpKVzGPHJLxhxMIo+HS pRFWUISf X-Proofpoint-GUID: vcpUBfq92qWmrHh1_bnlYTxoguu_ltda X-Proofpoint-ORIG-GUID: vcpUBfq92qWmrHh1_bnlYTxoguu_ltda X-Authority-Analysis: v=2.4 cv=PNkP+eqC c=1 sm=1 tr=0 ts=68b94f99 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=yp4Pn_RnPQDUuFz1ZG8A:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-04_03,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300019 On 9/3/25 10:21 AM, 'Krzysztof Kozlowski' via kernel wrote: > On 03/09/2025 10:04, Sarthak Garg wrote: >> Due to board-specific hardware constraints particularly related >> to level shifter in this case the maximum frequency for SD High-Speed >> (HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD >> card in HS mode. >> >> This is achieved by introducing the `max-sd-hs-hz` property in the >> device tree, allowing the controller to operate within safe frequency >> limits for HS mode. >> > > Probably we will now replicate the same discussion... And it will be > happening every time you send the same and not reflect it in commit msg. > > Bindings say board setup, this commit msg says board config, but the > patch says SoC. This is not correct. Both are correct, looking at the problem from two perspectives. The bindings description mentions board-specific limitations (e.g. because "the board's electrical design does not allow one to achieve the full rated frequency that the SoC can otherwise do, in a stable way") Here the author tries to argue that almost all SM8550 boards are broken in this sense, because the reference design did not feature the required passive components, making most (derivative) designs sort of "broken by default" - and only some (if any?) vendors decided to go with the additional components required to lift this limitation. This in turn makes it fair to assume the developer experience would benefit from having the SD card high speed modes always work (with the slight speed cap which may not be required for the 1 or 2 designs that took the extra step) without each board DT creator having to track down this property separately. Konrad