Re: [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC)

["Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>]

On Wed, 5 Nov 2025, Niklas Cassel wrote:

> On Fri, Oct 24, 2025 at 08:50:46AM +0200, Vincent Guittot wrote:
> > On Wed, 22 Oct 2025 at 21:04, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > > > +     dw_pcie_dbi_ro_wr_en(pci);
> > > > +
> > > > +     val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
> > > > +     val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
> > > > +     dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
> > > > +
> > > > +     /*
> > > > +      * Set max payload supported, 256 bytes and
> > > > +      * relaxed ordering.
> > > > +      */
> > > > +     val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
> > > > +     val &= ~(PCI_EXP_DEVCTL_RELAX_EN |
> > > > +              PCI_EXP_DEVCTL_PAYLOAD |
> > > > +              PCI_EXP_DEVCTL_READRQ);
> > > > +     val |= PCI_EXP_DEVCTL_RELAX_EN |
> > > > +            PCI_EXP_DEVCTL_PAYLOAD_256B |
> > > > +            PCI_EXP_DEVCTL_READRQ_256B;
> > > > +     dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
> > >
> > > MPS and relaxed ordering should be configured by the PCI core.  Is
> > > there some s32g-specific restriction about these?
> > 
> > I will check with the team why they did that
> 
> Most likely, the reason is that, the PCI core does not set the MPS to the
> maximum supported MPS for the root port.

PCI core set/doesn't set MPS based on config. Perhaps try with 
CONFIG_PCIE_BUS_PERFORMANCE.

> So without that change, the port will use use 128B instead of 256B.
> 
> I assume that you should be able to drop (at least the MPS part) if this
> change gets accepted:
> https://lore.kernel.org/linux-pci/20251104165125.174168-1-18255117159@163.com/
> 
> 
> Kind regards,
> Niklas
> 

-- 
 i.