From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4FA422154F; Thu, 24 Apr 2025 08:44:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745484267; cv=none; b=Cmw8b8kWarNmde4vTVs8PWO8YzPfsa6M5eeWWmoHGktg6dAHBU4xZxWNqbOoMyTayFqQFc7XT1CH17oYdEeG18+kKYRPfRYboA374cr/UxiKQzekdahnW6tzGfDT2NOAT73Uujy/v17YvJXAeechwMvKeB3+LeLN78j9BBhPDPU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745484267; c=relaxed/simple; bh=LFKI/gAV5T9H7xC7knhI1XC1tjC1M7eiEQrYT+Vo8k0=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=HdT1oMq+22LrXL2MP1L8GGmsVFX1uHWHG9bXQED8h6RfyR0ZIxlMLzPnuC9uQTjrKiAMncQFqlgJmp54E80zxJDEonQJid7MmoO0zNnuilVz2EvTI6D4G8/Peuusp4WCtSEdppu0t7VxBw/gOfeR1uZgVHqT+G0YHXKeKCwJ/bk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XWrX6r25; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XWrX6r25" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5A39BC4CEEE; Thu, 24 Apr 2025 08:44:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745484267; bh=LFKI/gAV5T9H7xC7knhI1XC1tjC1M7eiEQrYT+Vo8k0=; h=Date:Subject:To:References:From:In-Reply-To:From; b=XWrX6r25FjODg6/UBD4UJska+JlPFl2DN7sttJTuSJcVHD+oSx9vLDtr0hrdEW56E KmCjvl4hNhgxpRognjdqr7fOsO5qbhPpRE1h4ezg2n9H36LFsidIlCY99pvEwi7n30 CyRajZHTsr+K/SOZRj8NGm2+r4V0XcCrOXTTaRMkxf9RRvbS5L8h+8CUEh4e1SII1o cY+lD0meqzc0FlVZb5Qn3Goxsnlwf/EpXo0XtpbSPx+bGE72OjBF+sbN4jqSuFpdqL UYx93Bses4uzQsbDkTGJjpe1/uUcf2BMZeaE3IsmohKaacYOU3VHnt3455fuChzFAG Imi/BzjYQI/Hw== Message-ID: Date: Thu, 24 Apr 2025 10:44:23 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices To: Rengarajan S , kumaravel.thiagarajan@microchip.com, tharunkumar.pasumarthi@microchip.com, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, unglinuxdriver@microchip.com References: <20250424035913.7673-1-rengarajan.s@microchip.com> Content-Language: en-US From: Jiri Slaby Autocrypt: addr=jirislaby@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 24. 04. 25, 5:59, Rengarajan S wrote: > Systems that issue PCIe hot reset requests during a suspend/resume > cycle cause PCI1XXXX device revisions prior to C0 to get its UART > configuration registers reset to hardware default values. This results > in device inaccessibility and data transfer failures. Starting with > Revision C0, support was added in the device hardware (via the Hot > Reset Disable Bit) to allow resetting only the PCIe interface and its > associated logic, but preserving the UART configuration during a hot > reset. This patch enables the hot reset disable feature during suspend/ > resume for C0 and later revisions of the device. > > v2 > Retained the original writel and simplified the hot reset condition > v1 > Initial Commit. This should have been under the --- line below. > Signed-off-by: Rengarajan S Reviewed-by: Jiri Slaby > --- vvvvv here > drivers/tty/serial/8250/8250_pci1xxxx.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) thanks, -- js suse labs