Re: [net-next PATCH v2] octeontx2-af: Add debugfs support to dump NIX TM topology

[Wojciech Drewek <wojciech.drewek@intel.com>]

On 28.05.2024 10:56, Anshumali Gaur wrote:
> This patch adds support to dump NIX transmit queue topology.
> There are multiple levels of scheduling/shaping supported by
> NIX and a packet traverses through multiple levels before sending
> the packet out. At each level, there are set of scheduling/shaping
> rules applied to a packet flow.
> 
> Each packet traverses through multiple levels
> SQ->SMQ->TL4->TL3->TL2->TL1 and these levels are mapped in a parent-child
> relationship.
> 
> This patch dumps the debug information related to all TM Levels in
> the following way.
> 
> Example:
> $ echo <nixlf> > /sys/kernel/debug/octeontx2/nix/tm_tree
> $ cat /sys/kernel/debug/octeontx2/nix/tm_tree
> 
> A more desriptive set of registers at each level can be dumped
> in the following way.
> 
> Example:
> $ echo <nixlf> > /sys/kernel/debug/octeontx2/nix/tm_topo
> $ cat /sys/kernel/debug/octeontx2/nix/tm_topo
> 
> Signed-off-by: Anshumali Gaur <agaur@marvell.com>
> ---
> v2:
>   - Addressed review comments given by Simon Horman
> 	1. Resolved indentation issues 
> 
>  .../net/ethernet/marvell/octeontx2/af/rvu.h   |   1 +
>  .../marvell/octeontx2/af/rvu_debugfs.c        | 370 ++++++++++++++++++
>  .../ethernet/marvell/octeontx2/af/rvu_reg.h   |   7 +
>  3 files changed, 378 insertions(+)
> 
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
> index 35834687e40f..3063a84a45ef 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
> @@ -76,6 +76,7 @@ struct rvu_debugfs {
>  	struct dump_ctx nix_cq_ctx;
>  	struct dump_ctx nix_rq_ctx;
>  	struct dump_ctx nix_sq_ctx;
> +	struct dump_ctx nix_tm_ctx;
>  	struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
>  	int npa_qsize_id;
>  	int nix_qsize_id;
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
> index 881d704644fb..272b9dd1acb6 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
> @@ -1603,6 +1603,372 @@ static void print_nix_cn10k_sq_ctx(struct seq_file *m,
>  		   (u64)sq_ctx->dropped_pkts);
>  }
>  
> +static void print_tm_tree(struct seq_file *m,
> +			  struct nix_aq_enq_rsp *rsp, u64 sq)
> +{
> +	struct nix_sq_ctx_s *sq_ctx = &rsp->sq;
> +	struct nix_hw *nix_hw = m->private;
> +	struct rvu *rvu = nix_hw->rvu;
> +	u16 p1, p2, p3, p4, schq;
> +	int blkaddr;
> +	u64 cfg;
> +
> +	blkaddr = nix_hw->blkaddr;
> +	schq = sq_ctx->smq;
> +
> +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_MDQX_PARENT(schq));
> +	p1 = FIELD_GET(NIX_AF_MDQ_PARENT_MASK, cfg);
> +
> +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_TL4X_PARENT(p1));
> +	p2 = FIELD_GET(NIX_AF_TL4_PARENT_MASK, cfg);
> +
> +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_TL3X_PARENT(p2));
> +	p3 = FIELD_GET(NIX_AF_TL3_PARENT_MASK, cfg);
> +
> +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_TL2X_PARENT(p3));
> +	p4 = FIELD_GET(NIX_AF_TL2_PARENT_MASK, cfg);
> +	seq_printf(m,
> +		   "SQ(%llu) -> SMQ(%u) -> TL4(%u) -> TL3(%u) -> TL2(%u) -> TL1(%u)\n",
> +		   sq, schq, p1, p2, p3, p4);
> +}
> +
> +/*dumps given tm_tree registers*/
> +static int rvu_dbg_nix_tm_tree_display(struct seq_file *m, void *unused)
> +{
> +	int qidx, nixlf, rc, id, max_id = 0;
> +	struct nix_hw *nix_hw = m->private;
> +	struct rvu *rvu = nix_hw->rvu;
> +	struct nix_aq_enq_req aq_req;
> +	struct nix_aq_enq_rsp rsp;
> +	struct rvu_pfvf *pfvf;
> +	u16 pcifunc;
> +
> +	nixlf = rvu->rvu_dbg.nix_tm_ctx.lf;
> +	id = rvu->rvu_dbg.nix_tm_ctx.id;
> +
> +	if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc))
> +		return -EINVAL;
> +
> +	pfvf = rvu_get_pfvf(rvu, pcifunc);
> +	max_id = pfvf->sq_ctx->qsize;
> +
> +	memset(&aq_req, 0, sizeof(struct nix_aq_enq_req));
> +	aq_req.hdr.pcifunc = pcifunc;
> +	aq_req.ctype = NIX_AQ_CTYPE_SQ;
> +	aq_req.op = NIX_AQ_INSTOP_READ;
> +	seq_printf(m, "pcifunc is 0x%x\n", pcifunc);
> +	for (qidx = id; qidx < max_id; qidx++) {
> +		aq_req.qidx = qidx;
> +		rc = rvu_mbox_handler_nix_aq_enq(rvu, &aq_req, &rsp);
> +
> +		/* Skip SQ's if not initialized */
> +		if (!test_bit(qidx, pfvf->sq_bmap))
> +			continue;

Maybe this test should be the first thing we do in the loop or calling
rvu_mbox_handler_nix_aq_enq is required for this test to work?

> +
> +		if (rc) {
> +			seq_printf(m, "Failed to read SQ(%d) context\n",
> +				   aq_req.qidx);
> +			continue;
> +		}
> +		print_tm_tree(m, &rsp, aq_req.qidx);
> +	}
> +	return 0;
> +}
> +
> +static ssize_t rvu_dbg_nix_tm_tree_write(struct file *filp,
> +					 const char __user *buffer,
> +					 size_t count, loff_t *ppos)
> +{
> +	struct seq_file *m = filp->private_data;
> +	struct nix_hw *nix_hw = m->private;
> +	struct rvu *rvu = nix_hw->rvu;
> +	struct rvu_pfvf *pfvf;
> +	u16 pcifunc;
> +	u64 nixlf;
> +	int ret;
> +
> +	ret = kstrtoull_from_user(buffer, count, 10, &nixlf);
> +	if (ret)
> +		return ret;
> +
> +	if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc)) {
> +		ret = -EINVAL;
> +		goto done;
> +	}
> +
> +	pfvf = rvu_get_pfvf(rvu, pcifunc);
> +	if (!pfvf->sq_ctx) {
> +		dev_warn(rvu->dev, "SQ context is not initialized\n");
> +		ret = -EINVAL;
> +		goto done;
> +	}
> +	rvu->rvu_dbg.nix_tm_ctx.lf = nixlf;
> +done:
> +	return ret ? ret : count;

I don't think we need goto here, just return err code under each if statement
and return count at the end.

> +}
> +
> +RVU_DEBUG_SEQ_FOPS(nix_tm_tree, nix_tm_tree_display, nix_tm_tree_write);
> +

<...>

> +
> +/*dumps given tm_topo registers*/
> +static int rvu_dbg_nix_tm_topo_display(struct seq_file *m, void *unused)
> +{
> +	struct nix_hw *nix_hw = m->private;
> +	struct rvu *rvu = nix_hw->rvu;
> +	struct nix_aq_enq_req aq_req;
> +	struct nix_txsch *txsch;
> +	int nixlf, lvl, schq;
> +	u16 pcifunc;
> +
> +	nixlf = rvu->rvu_dbg.nix_tm_ctx.lf;
> +
> +	if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc))
> +		return -EINVAL;
> +
> +	memset(&aq_req, 0, sizeof(struct nix_aq_enq_req));
> +	aq_req.hdr.pcifunc = pcifunc;
> +	aq_req.ctype = NIX_AQ_CTYPE_SQ;
> +	aq_req.op = NIX_AQ_INSTOP_READ;
> +	seq_printf(m, "pcifunc is 0x%x\n", pcifunc);
> +
> +	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
> +		txsch = &nix_hw->txsch[lvl];
> +		for (schq = 0; schq < txsch->schq.max; schq++) {
> +			if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) == pcifunc)
> +				print_tm_topo(m, schq, lvl);
> +		}
> +	}
> +	return 0;
> +}
> +
> +static ssize_t rvu_dbg_nix_tm_topo_write(struct file *filp,
> +					 const char __user *buffer,
> +					 size_t count, loff_t *ppos)
> +{
> +	struct seq_file *m = filp->private_data;
> +	struct nix_hw *nix_hw = m->private;
> +	struct rvu *rvu = nix_hw->rvu;
> +	struct rvu_pfvf *pfvf;
> +	u16 pcifunc;
> +	u64 nixlf;
> +	int ret;
> +
> +	ret = kstrtoull_from_user(buffer, count, 10, &nixlf);
> +	if (ret)
> +		return ret;
> +
> +	if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc)) {
> +		ret = -EINVAL;
> +		goto done;
> +	}
> +
> +	pfvf = rvu_get_pfvf(rvu, pcifunc);
> +	if (!pfvf->sq_ctx) {
> +		dev_warn(rvu->dev, "SQ context is not initialized\n");
> +		ret = -EINVAL;
> +		goto done;
> +	}
> +	rvu->rvu_dbg.nix_tm_ctx.lf = nixlf;
> +done:
> +	return ret ? ret : count;

Same, no need for goto

> +}
> +
> +RVU_DEBUG_SEQ_FOPS(nix_tm_topo, nix_tm_topo_display, nix_tm_topo_write);
> +
>  /* Dumps given nix_sq's context */
>  static void print_nix_sq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)
>  {
> @@ -2349,6 +2715,10 @@ static void rvu_dbg_nix_init(struct rvu *rvu, int blkaddr)
>  		nix_hw = &rvu->hw->nix[1];
>  	}
>  
> +	debugfs_create_file("tm_tree", 0600, rvu->rvu_dbg.nix, nix_hw,
> +			    &rvu_dbg_nix_tm_tree_fops);
> +	debugfs_create_file("tm_topo", 0600, rvu->rvu_dbg.nix, nix_hw,
> +			    &rvu_dbg_nix_tm_topo_fops);
>  	debugfs_create_file("sq_ctx", 0600, rvu->rvu_dbg.nix, nix_hw,
>  			    &rvu_dbg_nix_sq_ctx_fops);
>  	debugfs_create_file("rq_ctx", 0600, rvu->rvu_dbg.nix, nix_hw,
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
> index 086f05c0376f..5ec92654e7ad 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
> @@ -429,6 +429,8 @@
>  #define NIX_AF_RX_ACTIVE_CYCLES_PCX(a)	(0x4800 | (a) << 16)
>  #define NIX_AF_LINKX_CFG(a)		(0x4010 | (a) << 17)
>  #define NIX_AF_MDQX_IN_MD_COUNT(a)	(0x14e0 | (a) << 16)
> +#define NIX_AF_SMQX_STATUS(a)		(0x730 | (a) << 16)
> +#define NIX_AF_MDQX_OUT_MD_COUNT(a)	(0xdb0 | (a) << 16)
>  
>  #define NIX_PRIV_AF_INT_CFG		(0x8000000)
>  #define NIX_PRIV_LFX_CFG		(0x8000010)
> @@ -442,6 +444,11 @@
>  #define NIX_CONST_MAX_BPIDS		GENMASK_ULL(23, 12)
>  #define NIX_CONST_SDP_CHANS		GENMASK_ULL(11, 0)
>  
> +#define NIX_AF_MDQ_PARENT_MASK         GENMASK_ULL(24, 16)
> +#define NIX_AF_TL4_PARENT_MASK         GENMASK_ULL(23, 16)
> +#define NIX_AF_TL3_PARENT_MASK         GENMASK_ULL(23, 16)
> +#define NIX_AF_TL2_PARENT_MASK         GENMASK_ULL(20, 16)
> +
>  /* SSO */
>  #define SSO_AF_CONST			(0x1000)
>  #define SSO_AF_CONST1			(0x1008)