From: Paolo Bonzini <pbonzini@redhat.com>
To: Borislav Petkov <bp@alien8.de>,
Krish Sadhukhan <krish.sadhukhan@oracle.com>
Cc: kvm@vger.kernel.org, jmattson@google.com, tglx@linutronix.de,
mingo@redhat.com, x86@kernel.org,
sean.j.christopherson@intel.com, vkuznets@redhat.com,
wanpengli@tencent.com, joro@8bytes.org,
dave.hansen@linux.intel.com, luto@kernel.org,
peterz@infradead.org, linux-kernel@vger.kernel.org,
hpa@zytor.com
Subject: Re: [PATCH 1/4 v3] x86: AMD: Replace numeric value for SME CPUID leaf with a #define
Date: Sat, 12 Sep 2020 08:54:27 +0200 [thread overview]
Message-ID: <c11dee69-e5fe-ce7a-8912-17393d2e1452@redhat.com> (raw)
In-Reply-To: <20200911212131.GB4110@zn.tnic>
On 11/09/20 23:21, Borislav Petkov wrote:
> On Fri, Sep 11, 2020 at 07:25:58PM +0000, Krish Sadhukhan wrote:
>
> <-- patches need commit message.
>
> ...
>
>> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
>> index 62b137c3c97a..033c112e03fc 100644
>> --- a/arch/x86/kernel/cpu/scattered.c
>> +++ b/arch/x86/kernel/cpu/scattered.c
>> @@ -39,8 +39,8 @@ static const struct cpuid_bit cpuid_bits[] = {
>> { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
>> { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
>> { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
>> - { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 },
>> - { X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 },
>> + { X86_FEATURE_SME, CPUID_EAX, 0, CPUID_AMD_SME, 0 },
>> + { X86_FEATURE_SEV, CPUID_EAX, 1, CPUID_AMD_SME, 0 },
>
> So this one gets a name and all the others above don't?
>
> This fact should've given you a hint that there's no need for naming
> CPUID leafs - it is easier to grep CPU manuals by the values so you can
> drop this patch.
Also, there'd be confusion between the CPUID_* enum in
arch/x86/include/asm/cpufeature.h.
Paolo
next prev parent reply other threads:[~2020-09-12 6:54 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-11 19:25 [PATCH 0/4 v3] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
2020-09-11 19:25 ` [PATCH 1/4 v3] x86: AMD: Replace numeric value for SME CPUID leaf with a #define Krish Sadhukhan
2020-09-11 21:21 ` Borislav Petkov
2020-09-12 6:54 ` Paolo Bonzini [this message]
2020-09-11 19:25 ` [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature Krish Sadhukhan
2020-09-11 19:36 ` Dave Hansen
2020-09-11 20:10 ` Krish Sadhukhan
2020-09-11 20:58 ` Dave Hansen
2020-09-11 21:33 ` Borislav Petkov
2020-09-11 21:44 ` Tom Lendacky
2020-09-11 19:26 ` [PATCH 3/4 v3] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domnains Krish Sadhukhan
2020-09-11 19:26 ` [PATCH 4/4 v3] KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
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