From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sg-1-19.ptr.blmpb.com (sg-1-19.ptr.blmpb.com [118.26.132.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B6281FBE80 for ; Wed, 6 Aug 2025 09:31:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=118.26.132.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754472666; cv=none; b=BXfXzwnMSAd1mp/ebU0nDU7hQTL+pTGrAz/+jxrkpxcBFNQ0Kgc7KzI1IWo0NK3nuOzm384YPcRfZNA2q09jmAPketsqYuh7pEnR0Sm2TGT9daZAsOMKQfLfat0Cgjt71e0tpwE3xkcpLb3N1taABpHugG9jcsX1jNR1F8co2Uo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754472666; c=relaxed/simple; bh=//+yvW26+zhbDmaZWxXy/IPR8L73jsj5oGIYBEaDI/w=; h=To:In-Reply-To:Subject:Message-Id:Cc:Mime-Version:From:Date: References:Content-Type; b=ubHPe9IAuXX7kjwDiXarnNq8QQpuFjDWX8UOLtvaoOOG9Qkiu/OfFmCqFUPt76rn1ol7YEkwzFLMHs2PkvHnHi0eZUubW1dfIwkKLVdPvYc0INzYG/KoWs/q07Ul0nuftYX2GJTw8fHOpHMFiPfr8QokFkKjeYD2UVJbYUE3N/I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=lanxincomputing.com; spf=pass smtp.mailfrom=lanxincomputing.com; dkim=pass (2048-bit key) header.d=lanxincomputing-com.20200927.dkim.feishu.cn header.i=@lanxincomputing-com.20200927.dkim.feishu.cn header.b=nqR6yqPJ; arc=none smtp.client-ip=118.26.132.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=lanxincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lanxincomputing.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lanxincomputing-com.20200927.dkim.feishu.cn header.i=@lanxincomputing-com.20200927.dkim.feishu.cn header.b="nqR6yqPJ" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=lanxincomputing-com.20200927.dkim.feishu.cn; t=1754472539; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=fBUEwNprg52rGFcGYTZBrY1u6S9H9M004MLIbBJj4zA=; b=nqR6yqPJ9IuUJ5EGVoNsMq42MGUumel8Ig/PcFtLi2NqkgrPwrnNLVt7dIDv8uw3leUBNN o8kqsTHr/M5yOAMtSobqGZi4yMLANAiJe7nDlaQscVwYjWYd6ragFGQdMJ/PsquoZvRDUF 86Q1CYAIcnvmCaqQJkiaI7qyJtswgZPjnZodFI+tJthjrXELvnvaIzrFg/+TG8wNjLXDNT OfyCk2RWX0l4K/TbqpDGLPn6qJmBqnRFcl0QBiNYRkjSS8/luzvxOJOJ09bf9YNDfnnpEN kvWzN7hbHo3XS9YFnQYjsYRB4jJnETzLlN9uer1irXOS203VRV90vwHlJuoJJw== To: "Nick Hu" , , "Alexandre Ghiti" , , User-Agent: Mozilla Thunderbird Content-Transfer-Encoding: 7bit X-Lms-Return-Path: In-Reply-To: <20250806082726.8835-2-nick.hu@sifive.com> Received: from [127.0.0.1] ([116.237.111.137]) by smtp.feishu.cn with ESMTPS; Wed, 06 Aug 2025 17:28:57 +0800 Subject: Re: [PATCH v2 1/2] irqchip/riscv-imsic: Restore the IMSIC registers Message-Id: Content-Language: en-US X-Original-From: Nutty Liu Cc: "Thomas Gleixner" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 From: "Nutty Liu" Date: Wed, 6 Aug 2025 17:28:55 +0800 References: <20250806082726.8835-1-nick.hu@sifive.com> <20250806082726.8835-2-nick.hu@sifive.com> Content-Type: text/plain; charset=UTF-8 On 8/6/2025 4:27 PM, Nick Hu wrote: > When the system woken up from the low power state, the IMSIC might be in > the reset state. Therefore adding the CPU PM callbacks to restore the > IMSIC register when the cpu resume from the low power state. > > Signed-off-by: Nick Hu > Reviewed-by: Yong-Xuan Wang > Reviewed-by: Cyan Yang > Reviewed-by: Anup Patel > --- > drivers/irqchip/irq-riscv-imsic-early.c | 40 ++++++++++++++++++++----- > 1 file changed, 32 insertions(+), 8 deletions(-) Reviewed-by: Nutty Liu Thanks, Nutty > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c > index d9ae87808651..62bcbcae8bd4 100644 > --- a/drivers/irqchip/irq-riscv-imsic-early.c > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > @@ -7,6 +7,7 @@ > #define pr_fmt(fmt) "riscv-imsic: " fmt > #include > #include > +#include > #include > #include > #include > @@ -109,14 +110,8 @@ static void imsic_handle_irq(struct irq_desc *desc) > chained_irq_exit(chip, desc); > } > > -static int imsic_starting_cpu(unsigned int cpu) > +static void imsic_restore(void) > { > - /* Mark per-CPU IMSIC state as online */ > - imsic_state_online(); > - > - /* Enable per-CPU parent interrupt */ > - enable_percpu_irq(imsic_parent_irq, irq_get_trigger_type(imsic_parent_irq)); > - > /* Setup IPIs */ > imsic_ipi_starting_cpu(); > > @@ -128,6 +123,19 @@ static int imsic_starting_cpu(unsigned int cpu) > > /* Enable local interrupt delivery */ > imsic_local_delivery(true); > +} > + > +static int imsic_starting_cpu(unsigned int cpu) > +{ > + /* Mark per-CPU IMSIC state as online */ > + imsic_state_online(); > + > + /* Enable per-CPU parent interrupt */ > + enable_percpu_irq(imsic_parent_irq, > + irq_get_trigger_type(imsic_parent_irq)); > + > + /* Restore the imsic reg */ > + imsic_restore(); > > return 0; > } > @@ -143,6 +151,22 @@ static int imsic_dying_cpu(unsigned int cpu) > return 0; > } > > +static int imsic_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v) > +{ > + switch (cmd) { > + case CPU_PM_EXIT: > + /* Restore the imsic reg */ > + imsic_restore(); > + break; > + } > + > + return NOTIFY_OK; > +} > + > +static struct notifier_block imsic_pm_notifier_block = { > + .notifier_call = imsic_pm_notifier, > +}; > + > static int __init imsic_early_probe(struct fwnode_handle *fwnode) > { > struct irq_domain *domain; > @@ -180,7 +204,7 @@ static int __init imsic_early_probe(struct fwnode_handle *fwnode) > cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_IMSIC_STARTING, "irqchip/riscv/imsic:starting", > imsic_starting_cpu, imsic_dying_cpu); > > - return 0; > + return cpu_pm_register_notifier(&imsic_pm_notifier_block); > } > > static int __init imsic_early_dt_init(struct device_node *node, struct device_node *parent)