RE: [PATCH v8 11/16] cxl/pci: Unifi CXL trace logging for CXL Endpoints and CXL Ports

[Shiju Jose <shiju.jose@huawei.com>]

>-----Original Message-----
>From: Jonathan Cameron <jonathan.cameron@huawei.com>
>Sent: 23 April 2025 17:45
>To: Terry Bowman <terry.bowman@amd.com>
>Cc: linux-cxl@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
>pci@vger.kernel.org; nifan.cxl@gmail.com; dave@stgolabs.net;
>dave.jiang@intel.com; alison.schofield@intel.com; vishal.l.verma@intel.com;
>dan.j.williams@intel.com; bhelgaas@google.com; mahesh@linux.ibm.com;
>ira.weiny@intel.com; oohall@gmail.com; Benjamin.Cheatham@amd.com;
>rrichter@amd.com; nathan.fontenot@amd.com;
>Smita.KoralahalliChannabasappa@amd.com; lukas@wunner.de;
>ming.li@zohomail.com; PradeepVineshReddy.Kodamati@amd.com; Shiju Jose
><shiju.jose@huawei.com>
>Subject: Re: [PATCH v8 11/16] cxl/pci: Unifi CXL trace logging for CXL Endpoints
>and CXL Ports
>
>On Wed, 26 Mar 2025 20:47:12 -0500
>Terry Bowman <terry.bowman@amd.com> wrote:
>
>Unify.
>
>
>> CXL currently has separate trace routines for CXL Port errors and CXL
>> Endpoint errors. This is inconvnenient for the user because they must
>> enable 2 sets of trace routines. Make updates to the trace logging
>> such that a single trace routine logs both CXL Endpoint and CXL Port
>> protocol errors.
>>
>> Also, CXL RAS errors are currently logged using the associated CXL
>> port's name returned from devname(). They are typically named with
>> 'port1', 'port2', etc. to indicate the hierarchial location in the CXL topology.
>> But, this doesn't clearly indicate the CXL card or slot reporting the
>> error.
>>
>> Update the logging to also log the corresponding PCIe devname. This
>> will give a PCIe SBDF or ACPI object name (in case of CXL HB). This
>> will provide details helping users understand which physical slot and
>> card has the error.
>>
>> Below is example output after making these changes.
>>
>> Correctable error example output:
>> cxl_port_aer_correctable_error: device=port1 (0000:0c:00.0) parent=root0
>(pci0000:0c) status='Received Error From Physical Layer'
>>
>> Uncorrectable error example output:
>> cxl_port_aer_uncorrectable_error: device=port1 (0000:0c:00.0) parent=root0
>(pci0000:0c) status: 'Memory Byte Enable Parity Error' first_error: 'Memory
>Byte Enable Parity Error'
>
>I'm not sure the pcie parent is adding much... Why bother with that?
>
>Shiju, is this going to affect rasdaemon handling?

Hi Jonathan,

Yes. Renaming the existing fields in the trace events will result failure
while parsing the fields in the rasdaemon.

>
>I'd assume we can't just rename fields in the tracepoints and combining them
>will also presumably make a mess?
>
>Jonathan
>
[...]
>>

Thanks,
Shiju