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Tue, 6 Feb 2024 08:26:35 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 6 Feb 2024 08:26:35 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 6 Feb 2024 08:26:35 -0600 Received: from [10.24.69.14] (chandru.dhcp.ti.com [10.24.69.14]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 416EQVlE008028; Tue, 6 Feb 2024 08:26:32 -0600 Message-ID: Date: Tue, 6 Feb 2024 19:56:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] clk: keystone: sci-clk: Adding support for non contiguous clocks Content-Language: en-US To: "Kumar, Udit" , Kamlesh Gurudasani , Nishanth Menon CC: , , , , , , , , References: <20240206104357.3803517-1-u-kumar1@ti.com> <20240206131420.wtitflgav23jto2q@verbally> <871q9pzoiq.fsf@kamlesh.i-did-not-set--mail-host-address--so-tickle-me> From: CHANDRU DHAVAMANI In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On 06/02/24 19:45, Kumar, Udit wrote: > > On 2/6/2024 7:24 PM, Kamlesh Gurudasani wrote: >> Nishanth Menon writes: >> >>> On 16:13-20240206, Udit Kumar wrote: >>>> Most of clocks and their parents are defined in contiguous range, >>>> But in few cases, there is gap in clock numbers[0]. >>>> Driver assumes clocks to be in contiguous range, and add their clock >>>> ids incrementally. >>>> >>>> New firmware started returning error while calling get_freq and is_on >>>> API for non-available clock ids. >>>> >>>> In this fix, driver checks and adds only valid clock ids. >>>> >>>> Fixes: 3c13933c6033 ("clk: keystone: sci-clk: add support for >>>> dynamically probing clocks") >>>> >>>> [0] >>>> https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html >>>> >>>> Section Clocks for NAVSS0_CPTS_0 Device, >>>> clock id 12-15 not present. >>>> >>>> Signed-off-by: Udit Kumar >>>>                   while (num_parents--) { >>>> +                    /* Check if this clock id is valid */ >>>> +                    ret = provider->ops->get_freq(provider->sci, >>>> +                        sci_clk->dev_id, clk_id, &freq); >>> get_freq is a bit expensive as it has to walk the clock tree to find >>> the clock frequency (at least the first time?). just wondering if >>> there is lighter alternative here? >>> >> How about get_clock? Doesn't read the registers at least. > > Said API needs, some flags to be passed, > > Can those flag be set to zero, Chandru ? get_clock doesn't require any flags to be passed. > > >> Regards, >> Kamlesh