From: Lino Sanfilippo <LinoSanfilippo@gmx.de>
To: Florian Fainelli <f.fainelli@gmail.com>, Andrew Lunn <andrew@lunn.ch>
Cc: davem@davemloft.net, charrer@alacritech.com, liodot@gmail.com,
gregkh@linuxfoundation.org, devel@driverdev.osuosl.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org
Subject: Re: [net-next 1/2] net: ethernet: slicoss: add slicoss gigabit ethernet driver
Date: Tue, 15 Nov 2016 23:54:43 +0100 [thread overview]
Message-ID: <c645c726-dbe2-108d-c79a-d8db350a13b8@gmx.de> (raw)
In-Reply-To: <41c0c732-0935-1625-b88d-c084e5000a6c@gmail.com>
On 15.11.2016 23:39, Florian Fainelli wrote:
> On 11/15/2016 02:34 PM, Lino Sanfilippo wrote:
>> On 15.11.2016 22:59, Andrew Lunn wrote:
>>>> The link state is retrieved by a command to the application processor that is running
>>>> on the network card. Also the register to set the phy configuration is write-only, so
>>>> it is not even possible to do the usual mdio bit-banging in the Phy read() and write()
>>>> functions (however there seems to be another application processor command reserved
>>>> for retrieving the PHY settings, but I have not tried it yet).
>>>
>>>>> + val = MII_BMCR << 16 | SLIC_PCR_AUTONEG |
>>>>> + SLIC_PCR_AUTONEG_RST;
>>>>> + slic_write(sdev, SLIC_REG_WPHY, val);
>>>
>>> This actually looks a lot like an MDIO write operation. The upper 16
>>> bits are the register, and the lower 16 bits are the data. What you
>>> don't have is the address. But maybe it is limited to one address.
>>>
>>> If the processor command reserved for read works in a similar way, you
>>> have enough to do an MDIO bus.
>>>
>>
>> Ok, I will give it a try. Reading values via the application processor
>> is a bit awkward though, since it requires an address to a dma area as part of
>> the command and then the AP informs the driver via irq that the dma memory has
>> been written. So probably the irq handler will have to set some flag and
>> the mdio_read() function will have to poll for that flag in place of doing
>> bit-banging a register.
>
> That's a bit unusual compared to typical controllers that are usually
> memory-mapped and that you can either write to, read/poll to know about
> completion. I suppose that you could still have a mdiobus implementation
> that is able to read to/from PHYs by submitting a command to the AP,
> wait on a completion structure, and have the interrupt handler do the
> completion of the command?
>
Thats essentially what I meant by setting a flag in the irq handler. The mdio
function would have to check somehow if the irq has been fired (be it by means
of a flag or a completion that is set by the irq handler and checked by the
mdio function). So I agree that it should work (if reading via the AP command
is actually possible).
Lino
next prev parent reply other threads:[~2016-11-15 22:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-13 4:47 Gigabit ethernet driver for Alacritechs SLIC devices Lino Sanfilippo
2016-11-13 4:47 ` [net-next 1/2] net: ethernet: slicoss: add slicoss gigabit ethernet driver Lino Sanfilippo
2016-11-13 7:13 ` kbuild test robot
2016-11-13 8:38 ` kbuild test robot
2016-11-13 19:55 ` Andrew Lunn
2016-11-15 20:46 ` Lino Sanfilippo
2016-11-15 20:54 ` Florian Fainelli
2016-11-15 21:24 ` Lino Sanfilippo
2016-11-15 21:59 ` Andrew Lunn
2016-11-15 22:34 ` Lino Sanfilippo
2016-11-15 22:39 ` Florian Fainelli
2016-11-15 22:54 ` Lino Sanfilippo [this message]
2016-11-15 23:03 ` Andrew Lunn
2016-11-15 23:14 ` Lino Sanfilippo
2016-11-24 12:30 ` Aw: " Lino Sanfilippo
2016-11-13 4:47 ` [net-next 2/2] MAINTAINERS: add entry for slicoss " Lino Sanfilippo
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