From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87843C2BB3F for ; Mon, 20 Nov 2023 04:21:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231836AbjKTEV4 (ORCPT ); Sun, 19 Nov 2023 23:21:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229470AbjKTEVx (ORCPT ); Sun, 19 Nov 2023 23:21:53 -0500 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A9C4C5; Sun, 19 Nov 2023 20:21:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700454110; x=1731990110; h=message-id:date:mime-version:cc:subject:to:references: from:in-reply-to:content-transfer-encoding; bh=6v/qk6XILJ+EShe/DB479gTNTuB+ktH4JpqYg6NOK44=; b=Gri5v89c3emaAYFCIIK4RTwo7EropjZxTtjHnru0JhnqlzVbE0g4HQcQ WR/Ae3/x7mvbx3nzRe6uCNlJ+yB/yoexsIn19utS9RhS9Ho7zBGvOtDgq h6byLIlwaxHgMUyp6F7ljw8Fi+urVjDDWmztcDs8w9/2G6UIs731kkZ1S 2Q9LA+WX32noRNyIMlILVymHAwEnwziTvFWD/bJlhdhh5qcFnVPxQSYOv f84dlK9qZ6smKg+vTEORGh+WgvWqBrAzXV2YF9B1lDtQGVykENmVd4SH4 3zejx7Esva3aic3xH02xSGIoP9arljI6Zt2ViECa1GvxgBsvMZ1w0d1il g==; X-IronPort-AV: E=McAfee;i="6600,9927,10899"; a="381939857" X-IronPort-AV: E=Sophos;i="6.04,212,1695711600"; d="scan'208";a="381939857" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2023 20:21:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10899"; a="716104605" X-IronPort-AV: E=Sophos;i="6.04,212,1695711600"; d="scan'208";a="716104605" Received: from allen-box.sh.intel.com (HELO [10.239.159.127]) ([10.239.159.127]) by orsmga003.jf.intel.com with ESMTP; 19 Nov 2023 20:21:46 -0800 Message-ID: Date: Mon, 20 Nov 2023 12:17:28 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: baolu.lu@linux.intel.com, "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , "Huang, Ying" , Alistair Popple , "Luo, Yuzhang" , "Zhu, Tony" Subject: Re: [PATCH 1/1] iommu/vt-d: Fix incorrect cache invalidation for mm notification Content-Language: en-US To: "Tian, Kevin" , Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe References: <20231117090933.75267-1-baolu.lu@linux.intel.com> From: Baolu Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/20/23 11:45 AM, Tian, Kevin wrote: >> From: Lu Baolu >> Sent: Friday, November 17, 2023 5:10 PM >> >> Commit 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when >> invalidating TLBs") moved the secondary TLB invalidations into the TLB >> invalidation functions to ensure that all secondary TLB invalidations >> happen at the same time as the CPU invalidation and added a flush-all >> type of secondary TLB invalidation for the batched mode, where a range >> of [0, -1UL) is used to indicates that the range extends to the end of >> the address space. >> >> However, using an end address of -1UL caused an overflow in the Intel >> IOMMU driver, where the end address was rounded up to the next page. >> As a result, both the IOTLB and device ATC were not invalidated correctly. >> >> Add a flush all helper function and call it when the invalidation range >> is from 0 to -1UL, ensuring that the entire caches are invalidated >> correctly. >> >> Fixes: 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when >> invalidating TLBs") >> Cc:stable@vger.kernel.org >> Cc: Huang Ying >> Cc: Alistair Popple >> Tested-by: Luo Yuzhang # QAT >> Tested-by: Tony Zhu # DSA >> Signed-off-by: Lu Baolu >> --- >> drivers/iommu/intel/svm.c | 26 ++++++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> >> diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c >> index 50a481c895b8..588385050a07 100644 >> --- a/drivers/iommu/intel/svm.c >> +++ b/drivers/iommu/intel/svm.c >> @@ -216,6 +216,27 @@ static void intel_flush_svm_range(struct intel_svm >> *svm, unsigned long address, >> rcu_read_unlock(); >> } >> >> +static void intel_flush_svm_all(struct intel_svm *svm) >> +{ >> + struct device_domain_info *info; >> + struct intel_svm_dev *sdev; >> + >> + rcu_read_lock(); >> + list_for_each_entry_rcu(sdev, &svm->devs, list) { >> + info = dev_iommu_priv_get(sdev->dev); >> + >> + qi_flush_piotlb(sdev->iommu, sdev->did, svm->pasid, 0, -1UL, >> 1); > Why setting 'ih' to skip invalidating page structure caches? It should be set to '0'. Good catch! Thank you! Best regards, baolu