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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b935ae666d6sm140619966b.37.2026.02.27.03.34.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Feb 2026 03:34:06 -0800 (PST) Message-ID: Date: Fri, 27 Feb 2026 12:34:04 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] drm/msm/dpu: fix mismatch between power and frequency To: Dmitry Baryshkov Cc: yuanjiey , robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, krzysztof.kozlowski@linaro.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com References: <20260109083808.1047-1-yuanjie.yang@oss.qualcomm.com> <20260109083808.1047-2-yuanjie.yang@oss.qualcomm.com> <4g6fyehdc3fejx3pzeysmghigazfei3jz2vmnvxrnqkkbtbxdb@bdlcddxlvbhl> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <4g6fyehdc3fejx3pzeysmghigazfei3jz2vmnvxrnqkkbtbxdb@bdlcddxlvbhl> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI3MDEwMCBTYWx0ZWRfX3XwHkoFJ2S1k MiaIWk1Hn1wtyqOuUo89L/pdmP1IsPQFsPssYvS9BGOd/96A8b4ULZHNICmPkulletnDvxKRFTf VYA1bGXupzUaZYP1ysC0FEEYvWAJbDVl3d8mgGxuwWinPFLS/W+xcZj5WVVVxD6HE9Cv2EK+P3a fgkyRLNBdjkEBWa124NGS/W8FujJxuECTDnbX5mUMfD+seqRbyShMB86OFrjrj1KC3SKHbp4x16 I/GyL3ACaeVvwRjg9r63zNxhzDrv/7FPSf3SUuscRnM3nBKQujNU03O89vpA7NEJMRTokWurwUX rs0q0k33r04ibUV7oxircjjruPIul17ttBDO4umjEmUXcJXieHyuNwSamrtsnOIr4xoC5RvRu75 kGenWOXhlmyFmJvxlgDOzSvqQKOWRg+gcQRZWIeM1xjSPApGn4ZMezaW7QQIJZw90uyrJv+U/5E CQFqqC59kq1DAWR3M3A== X-Proofpoint-GUID: 2hyA4nO7KMCKPajkLSdHxPcCZ6EEEFee X-Authority-Analysis: v=2.4 cv=bIsb4f+Z c=1 sm=1 tr=0 ts=69a18131 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Og81VDND5z1jpqFtuisA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-ORIG-GUID: 2hyA4nO7KMCKPajkLSdHxPcCZ6EEEFee X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-27_01,2026-02-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 malwarescore=0 bulkscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602270100 On 2/27/26 4:48 AM, Dmitry Baryshkov wrote: > On Thu, Feb 26, 2026 at 02:35:52PM +0100, Konrad Dybcio wrote: >> On 1/12/26 9:25 AM, yuanjiey wrote: >>> On Mon, Jan 12, 2026 at 09:38:41AM +0200, Dmitry Baryshkov wrote: >>>> On Mon, 12 Jan 2026 at 08:23, yuanjiey wrote: >>>>> >>>>> On Fri, Jan 09, 2026 at 05:22:37PM +0200, Dmitry Baryshkov wrote: >>>>>> On Fri, Jan 09, 2026 at 04:38:07PM +0800, yuanjie yang wrote: >>>>>>> From: Yuanjie Yang [...] > Please correct me if I'm wrong, if we drop dev_pm_opp_set() from > dpu_runtime_suspend, then we should be able to also skip setting OPP > corner in dpu_runtime_resume(), because the previously set corner should > be viable until drm/msm driver commits new state / new modes. That matches my understanding. > The only important issue is to set the corner before starting up the > DPU, where we already have code to set MDP_CLK to the max frequency. > > Which means, we only need to drop the dev_pm_set_rate call from the > dpu_runtime_suspend(). I concur. >> For MDSS, we're currently generally describing the MDSS_AHB clock, the >> GCC_AHB clock and the MDP clock (sounds wrong?) - there's not even an OPP > > No. As far as I remember, MDP_CLK is necessary to access MDSS registers > (see commit d2570ee67a47 ("drm/msm/mdss: generate MDSS data for MDP5 > platforms")), I don't remember if accessing HW_REV without MDP_CLK > resulted in a zero reads or in a crash. At the same time it needs to be > enabled to any rate, which means that for most of the operations > msm_mdss.c can rely on DPU keeping the clock up and running. > >> table.. The GCC clock is sourced from (and scaled by) the NoC, but the >> MDSS_AHB one seems to have 3 actually configurable performance points >> that neither we nor seemingly the downstream driver seem to really care >> about (i.e. both just treat it as on/off). If we need to scale it, we >> should add an OPP table, if we don't, we should at least add required-opps. > > I think, dispcc already has a minimal vote on the MMCX, which fulfill > these needs. I have slightly mixed feelings, but I suppose that as we accepted Commit e3e56c050ab6 ("soc: qcom: rpmhpd: Make power_on actually enable the domain"), we can generally agree that it makes sense that calling genpd->on() actually turns on the power indeed What I'm worried about is if the clock is pre-configured to run at a high frequency from the bootloader (prepare_enable only sets the EN bit in the RCG, and doesn't impact the state of M/N/D at a glance), we may get a brownout This rings the "downstream really did it better with putting clock dvfs states into the clk driver" bell, but I suppose the way to fight this would be to simply set_rate(fmax) there too.. I attempted an experiment with pulling out the plug. MMCX enabled with the AHB clock off results in a read-as-zero. I tried really hard to disable the mdp clock, but it seems like the "shared_ops" reflect some sort of "you *really* can't just disable it" type behavior (verified with debugcc) There's a possible race condition if we don't do it: ------- bootloader -------- configure display, mdp_clk=turbo ------- linux ------------- load rpmhpd | load venus | set mmcx=lowsvs | mdp_clk is @ turbo | brownout | | *but* that should be made impossible because of .sync_state(). This may impact hacky setups like simplefb, but as the name implies, that's hacky. Relying on .sync_state() however will not cover the case if the mdss module is removed and re-inserted later, possibly with mmcx disabled entirely but the clock not parked at a sufficiently low rate. TLDR: reassess whether MDSS needs the MDP clock, if so, we should just plug the MDP opp table into it and set_rate(fmax) during mdss init >> The MDP4/MDP5 drivers are probably wrong too in this regard, but many >> targets supported by these may not even have OPP tables and are generally >> not super high priority for spending time on.. that can, I'd kick down the >> road unless someone really wants to step up > > I'd really not bother with those two drivers, unless we start seing > crashes. For MDP4 platforms we don't implement power domains at all, no > interconnects, etc., which means that the system will never go to a > lower power state. Right. Might be that 2030-something arrives and armv7 is gone before someone randomly decides to work on that! > MDP5 platforms mostly don't have OPP tables. (I'm not counting MSM8998 / > SDM630 / SDM660 here). MSM8917 / MSM8937 have only DSI tables, MSM8976 > has both MDP and DSI tables (my favourite MSM8996 has none). Probably we > should start there by adding missing bits adding corresponding > dev_pm_set_rate() calls as required (as demostrated by the DPU driver). A bit off-topic, but: drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 1101: { .revision = 0, .config = { .hw = &msm8x74v1_config } }, 1102: { .revision = 1, .config = { .hw = &msm8x26_config } }, 1103: { .revision = 2, .config = { .hw = &msm8x74v2_config } }, 1104: { .revision = 3, .config = { .hw = &apq8084_config } }, 1105: { .revision = 6, .config = { .hw = &msm8x16_config } }, 1106: { .revision = 8, .config = { .hw = &msm8x36_config } }, 1107: { .revision = 9, .config = { .hw = &msm8x94_config } }, 1108: { .revision = 7, .config = { .hw = &msm8x96_config } }, 1109: { .revision = 11, .config = { .hw = &msm8x76_config } }, 1110: { .revision = 14, .config = { .hw = &msm8937_config } }, 1111: { .revision = 15, .config = { .hw = &msm8917_config } }, 1112: { .revision = 16, .config = { .hw = &msm8x53_config } }, 96 is in DPU. any other candidates that should be moved over? > A note to myself to also add OPP tables support to the HDMI driver. Eliza! Konrad