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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: Wd1Fr01ad6BaqVVcpETaucuUe2P5I98L X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI1MDA0NiBTYWx0ZWRfXwG/jRsqB9MWY dmIstIkn0UpQw3/2GE4aPOa/ZGdFhMrmTGomLO8NQisqvFoVZ/kGXrnvwsmYmKOA/tbQ9dOYO1t 77z1r/4Xax3AuzHtPUWB54Qz8F2fGYvez8PMj3eagZyOH5gGrc9yhHuY5mu0lly5ICxSJlvhB7x PwMPrIRy1H28qqKASkSB7eJeNWS4a6bW5NQZDGye39KwO3UaVx1742s0/P6LH/ijoQ6ofx8liE7 NieIDc+25d+VQ/ikwuL34moYe6Jv6o+YH6nDyCYW37xLc3jJqj8N1bRulM0O3GHDySkOkmc3/89 Klafljt5R/Qz8ky6YBPlSd/6HUux4nVcnQpdhorbhAt18alNqPB4RtTK3Ra1+uDdRA63OLobXrG K3mp8AODgJlaqM9Jh498XFcUq1MIUJa0kz2lrZnlPCJ1YGlOqF8kezefWUFHRV9W0W+dh2B+WVU 3NjVmnVqXVOQWUIbOoQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI1MDA0NiBTYWx0ZWRfX6BfdB/9w6uLX z0iMxWzL0b9CMIfZsLAOEC4WMVgP66802hYoM7g4dyUMKw3GCoed51kF642C8OTSIihKVcmMha8 Jl5hTsDB6KOQzQD4qHCofNe7iuTB4qs= X-Authority-Analysis: v=2.4 cv=L7ItheT8 c=1 sm=1 tr=0 ts=6a8d2b16 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=JOUT_JFrYYanlDGIWxUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: Wd1Fr01ad6BaqVVcpETaucuUe2P5I98L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-25_01,2026-08-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 impostorscore=0 spamscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608250046 On 8/12/2026 6:33 PM, Manivannan Sadhasivam wrote: > On Wed, Aug 12, 2026 at 11:25:12AM +0530, Sushrut Shree Trivedi wrote: > > [...] > >>>> + #include >>>> + >>>> + soc { >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>> Get rid of 'soc' node. >> If we remove soc node, dt-schema uses address-cells = <1>, >> size-cells  = <1> for dt-binding check and throws errors. >> >> Do you suggest ignoring those errors ? > No, you need to make the 'reg' entries 1 cell. As discussed separately, since we have a 64 bit BAR region specified inside ranges, we need the soc node and the associated address-cells, size-cells update to avoid dt-binding errors. > >>>> + pcie@45e8000 { >>>> + device_type = "pci"; >>>> + compatible = "qcom,shikra-pcie"; >>>> + reg = <0x0 0x045e8000 0x0 0x3000>, >>>> + <0x0 0x60000000 0x0 0xf1d>, >>>> + <0x0 0x60000f20 0x0 0xa8>, >>>> + <0x0 0x60001000 0x0 0x1000>, >>>> + <0x0 0x60100000 0x0 0x100000>, >>>> + <0x0 0x045eb000 0x0 0x1000>; >>>> + reg-names = "parf", >>>> + "dbi", >>>> + "elbi", >>>> + "atu", >>>> + "config", >>>> + "mhi"; >>>> + #address-cells = <3>; >>>> + #size-cells = <2>; >>>> + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, >>>> + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>, >>>> + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x0000000>; >>>> + bus-range = <0x00 0xff>; >>>> + >>>> + linux,pci-domain = <0>; >>>> + num-lanes = <1>; >>>> + >>>> + interrupts = , >>>> + , >>>> + , >>>> + , >>>> + , >>>> + , >>>> + , >>>> + , >>>> + ; >>>> + interrupt-names = "msi0", >>>> + "msi1", >>>> + "msi2", >>>> + "msi3", >>>> + "msi4", >>>> + "msi5", >>>> + "msi6", >>>> + "msi7", >>>> + "global"; >>>> + >>>> + interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>, >>>> + <0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>, >>>> + <0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>, >>>> + <0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>; >>>> + interrupt-map-mask = <0 0 0 0x7>; >>>> + #interrupt-cells = <1>; >>>> + >>>> + clocks = <&gcc GCC_PCIE_AUX_CLK>, >>>> + <&gcc GCC_PCIE_CFG_AHB_CLK>, >>>> + <&gcc GCC_PCIE_MSTR_AXI_CLK>, >>>> + <&gcc GCC_PCIE_SLV_AXI_CLK>, >>>> + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, >>>> + <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>, >>>> + <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>, >>>> + <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>; >>>> + clock-names = "aux", >>>> + "cfg", >>>> + "bus_master", >>>> + "bus_slave", >>>> + "slave_q2a", >>>> + "ddrss_memnoc_pcie", >>>> + "tile", >>>> + "qmip_pcie_ahb"; >>>> + >>>> + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; >>>> + assigned-clock-rates = <19200000>; >>>> + >>>> + interconnects = <&system_noc MASTER_PCIE2_0 RPM_ALWAYS_TAG >>>> + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, >>>> + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG >>>> + &config_noc SLAVE_PCIE2_0 RPM_ACTIVE_TAG>; >>>> + >>>> + interconnect-names = "pcie-mem", >>>> + "cpu-pcie"; >>>> + >>>> + iommu-map = <0x0 &apps_smmu 0x800 0x1>, >>>> + <0x100 &apps_smmu 0x801 0x1>; >>>> + >>>> + resets = <&gcc GCC_PCIE_BCR>; >>>> + reset-names = "pci"; >>>> + >>>> + power-domains = <&gcc GCC_PCIE_GDSC>; >>>> + >>>> + max-link-speed = <2>; >>> You don't need 'max-link-speed' unless you want to limit the link speed. >> This is needed since Shikra controller supports Gen3 but the PHY >> is only capable of Gen2. Without limiting the speed, link-up fails. > This is a critical limitation that should've been mentioned in the commit > message. > > - Mani ACK >