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From: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
To: "daniel@ffwll.ch" <daniel@ffwll.ch>,
	"Winkler, Tomas" <tomas.winkler@intel.com>,
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	"airlied@linux.ie" <airlied@linux.ie>
Cc: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
	"Lubart, Vitaly" <vitaly.lubart@intel.com>,
	"Usyskin, Alexander" <alexander.usyskin@intel.com>,
	"joonas.lahtinen@linux.intel.com"
	<joonas.lahtinen@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"tvrtko.ursulin@linux.intel.com" <tvrtko.ursulin@linux.intel.com>,
	"Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>,
	"jani.nikula@linux.intel.com" <jani.nikula@linux.intel.com>
Subject: Re: [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM
Date: Thu, 1 Sep 2022 16:31:06 +0000	[thread overview]
Message-ID: <cb7cef1bb0bbd5aa07f2023ed3c4e4003f810819.camel@intel.com> (raw)
In-Reply-To: <20220806122636.43068-15-tomas.winkler@intel.com>

This patch hasnt changed since v5 and i already provided the R-b then so re-posting rb so patchworks can pick it up:

Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>


On Sat, 2022-08-06 at 15:26 +0300, Winkler, Tomas wrote:
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resource to the auxiliary data of the child device.
> 
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gsc.c | 91 ++++++++++++++++++++++++++---
>  drivers/gpu/drm/i915/gt/intel_gsc.h |  3 +
>  2 files changed, 87 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index e1040c8f2fd3..162bea57fbb5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -7,6 +7,7 @@
>  #include <linux/mei_aux.h>
>  #include "i915_drv.h"
>  #include "i915_reg.h"
> +#include "gem/i915_gem_region.h"
>  #include "gt/intel_gsc.h"
>  #include "gt/intel_gt.h"
>  
> @@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
>  	return irq_set_chip_data(irq, NULL);
>  }
>  
> +static int
> +gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
> +{
> +	struct intel_gt *gt = gsc_to_gt(gsc);
> +	struct drm_i915_gem_object *obj;
> +	void *vaddr;
> +	int err;
> +
> +	obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
> +	if (IS_ERR(obj)) {
> +		drm_err(&gt->i915->drm, "Failed to allocate gsc memory\n");
> +		return PTR_ERR(obj);
> +	}
> +
> +	err = i915_gem_object_pin_pages_unlocked(obj);
> +	if (err) {
> +		drm_err(&gt->i915->drm, "Failed to pin pages for gsc memory\n");
> +		goto out_put;
> +	}
> +
> +	vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
> +	if (IS_ERR(vaddr)) {
> +		err = PTR_ERR(vaddr);
> +		drm_err(&gt->i915->drm, "Failed to map gsc memory\n");
> +		goto out_unpin;
> +	}
> +
> +	memset(vaddr, 0, obj->base.size);
> +
> +	i915_gem_object_unpin_map(obj);
> +
> +	intf->gem_obj = obj;
> +
> +	return 0;
> +
> +out_unpin:
> +	i915_gem_object_unpin_pages(obj);
> +out_put:
> +	i915_gem_object_put(obj);
> +	return err;
> +}
> +
> +static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
> +{
> +	struct drm_i915_gem_object *obj = fetch_and_zero(&intf->gem_obj);
> +
> +	if (!obj)
> +		return;
> +
> +	if (i915_gem_object_has_pinned_pages(obj))
> +		i915_gem_object_unpin_pages(obj);
> +
> +	i915_gem_object_put(obj);
> +}
> +
>  struct gsc_def {
>  	const char *name;
>  	unsigned long bar;
>  	size_t bar_size;
>  	bool use_polling;
>  	bool slow_firmware;
> +	size_t lmem_size;
>  };
>  
>  /* gsc resources and definitions (HECI1 and HECI2) */
> @@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] = {
>  		.name = "mei-gsc",
>  		.bar = DG2_GSC_HECI1_BASE,
>  		.bar_size = GSC_BAR_LENGTH,
> +		.lmem_size = SZ_4M,
>  	},
>  	{
>  		.name = "mei-gscfi",
> @@ -90,26 +148,32 @@ static void gsc_release_dev(struct device *dev)
>  	kfree(adev);
>  }
>  
> -static void gsc_destroy_one(struct intel_gsc_intf *intf)
> +static void gsc_destroy_one(struct drm_i915_private *i915,
> +			    struct intel_gsc *gsc, unsigned int intf_id)
>  {
> +	struct intel_gsc_intf *intf = &gsc->intf[intf_id];
> +
>  	if (intf->adev) {
>  		auxiliary_device_delete(&intf->adev->aux_dev);
>  		auxiliary_device_uninit(&intf->adev->aux_dev);
>  		intf->adev = NULL;
>  	}
> +
>  	if (intf->irq >= 0)
>  		irq_free_desc(intf->irq);
>  	intf->irq = -1;
> +
> +	gsc_ext_om_destroy(intf);
>  }
>  
> -static void gsc_init_one(struct drm_i915_private *i915,
> -			 struct intel_gsc_intf *intf,
> +static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
>  			 unsigned int intf_id)
>  {
>  	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>  	struct mei_aux_device *adev;
>  	struct auxiliary_device *aux_dev;
>  	const struct gsc_def *def;
> +	struct intel_gsc_intf *intf = &gsc->intf[intf_id];
>  	int ret;
>  
>  	intf->irq = -1;
> @@ -141,7 +205,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
>  	intf->irq = irq_alloc_desc(0);
>  	if (intf->irq < 0) {
>  		drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
> -		return;
> +		goto fail;
>  	}
>  
>  	ret = gsc_irq_init(intf->irq);
> @@ -155,6 +219,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
>  	if (!adev)
>  		goto fail;
>  
> +	if (def->lmem_size) {
> +		drm_dbg(&i915->drm, "setting up GSC lmem\n");
> +
> +		if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
> +			drm_err(&i915->drm, "setting up gsc extended operational memory failed\n");
> +			kfree(adev);
> +			goto fail;
> +		}
> +
> +		adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
> +		adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
> +	}
> +
>  	adev->irq = intf->irq;
>  	adev->bar.parent = &pdev->resource[0];
>  	adev->bar.start = def->bar + pdev->resource[0].start;
> @@ -188,7 +265,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
>  
>  	return;
>  fail:
> -	gsc_destroy_one(intf);
> +	gsc_destroy_one(i915, gsc, intf->id);
>  }
>  
>  static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
> @@ -229,7 +306,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
>  		return;
>  
>  	for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
> -		gsc_init_one(i915, &gsc->intf[i], i);
> +		gsc_init_one(i915, gsc, i);
>  }
>  
>  void intel_gsc_fini(struct intel_gsc *gsc)
> @@ -241,5 +318,5 @@ void intel_gsc_fini(struct intel_gsc *gsc)
>  		return;
>  
>  	for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
> -		gsc_destroy_one(&gsc->intf[i]);
> +		gsc_destroy_one(gt->i915, gsc, i);
>  }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h
> index 68582f912b21..fcac1775e9c3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.h
> @@ -20,11 +20,14 @@ struct mei_aux_device;
>  
>  /**
>   * struct intel_gsc - graphics security controller
> + *
> + * @gem_obj: scratch memory GSC operations
>   * @intf : gsc interface
>   */
>  struct intel_gsc {
>  	struct intel_gsc_intf {
>  		struct mei_aux_device *adev;
> +		struct drm_i915_gem_object *gem_obj;
>  		int irq;
>  		unsigned int id;
>  	} intf[INTEL_GSC_NUM_INTERFACES];
> -- 
> 2.37.1
> 


  reply	other threads:[~2022-09-01 16:31 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-06 12:26 [PATCH v7 00/15] GSC support for XeHP SDV and DG2 Tomas Winkler
2022-08-06 12:26 ` [PATCH v7 01/15] drm/i915/gsc: skip irq initialization if using polling Tomas Winkler
2022-08-06 12:26 ` [PATCH v7 02/15] mei: add kdoc for struct mei_aux_device Tomas Winkler
2022-09-01 15:30   ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 03/15] mei: add slow_firmware flag to the mei auxiliary device Tomas Winkler
2022-08-06 12:26 ` [PATCH v7 04/15] drm/i915/gsc: add slow_firmware flag to the gsc device definition Tomas Winkler
2022-08-06 12:26 ` [PATCH v7 05/15] drm/i915/gsc: add GSC XeHP SDV platform definition Tomas Winkler
2022-09-01 15:31   ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 06/15] mei: gsc: use polling instead of interrupts Tomas Winkler
2022-09-01 16:00   ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 07/15] mei: gsc: wait for reset thread on stop Tomas Winkler
2022-09-01 16:07   ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 08/15] mei: extend timeouts on slow devices Tomas Winkler
2022-09-01 17:00   ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 09/15] mei: bus: export common mkhi definitions into a separate header Tomas Winkler
2022-09-01 20:54   ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-09-03 10:05     ` Winkler, Tomas
2022-08-06 12:26 ` [PATCH v7 10/15] mei: mkhi: add memory ready command Tomas Winkler
2022-09-01 15:08   ` Greg Kroah-Hartman
2022-09-01 20:56   ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory Tomas Winkler
2022-09-01 21:02   ` Ceraolo Spurio, Daniele
2022-09-04  7:29     ` Usyskin, Alexander
2022-09-04 22:26       ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 12/15] mei: gsc: add transition to PXP mode in resume flow Tomas Winkler
2022-09-01 21:19   ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 13/15] mei: debugfs: add pxp mode to devstate in debugfs Tomas Winkler
2022-09-01 21:20   ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM Tomas Winkler
2022-09-01 16:31   ` Teres Alexis, Alan Previn [this message]
2022-09-02  8:25   ` [Intel-gfx] " Matthew Auld
2022-08-06 12:26 ` [PATCH v7 15/15] HAX: drm/i915: force INTEL_MEI_GSC on for CI Tomas Winkler
2022-09-01 15:09 ` [PATCH v7 00/15] GSC support for XeHP SDV and DG2 Greg Kroah-Hartman
2022-09-09 10:24   ` Joonas Lahtinen
2022-09-09 15:17     ` Ceraolo Spurio, Daniele
2022-09-09 16:33       ` Vivi, Rodrigo
2022-09-09 17:16         ` [Intel-gfx] " Lucas De Marchi
2022-09-12 12:51         ` Joonas Lahtinen

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