[PATCH v2 6/8] x86,fs/resctrl: Add support for Global Slow Memory Bandwidth Allocation

Babu Moger
2026-04-24T01:42:55Z

AMD PQoS Global Slow Memory Bandwidth Enforcement (GLSBE) is an extension
to GLBE that lets software specify slow-memory bandwidth limits for groups
of threads that span multiple QoS domains. GLSBE operates within the same
GLBE control domains defined by GLBE.

Like GLBE, the GLSBE control domain is by default aligned to the system's
NPS (Nodes Per Socket) configuration, a BIOS-level setting on AMD
processors that determines how many NUMA (Non-Uniform Memory Access) nodes
each CPU socket is divided into.

Support for GLSBE is indicated by CPUID leaf 0x80000020, ECX=0, EBX bit 8.
When this bit is set to 1, the platform supports GLSBE.

Because AMD Slow Memory Bandwidth Enforcement is exposed to resctrl as
SMBA, Global Slow Memory Bandwidth Enforcement is exposed as GSMBA to keep
the naming consistent.

Add following changes to support GLSBE:

- Add X86_FEATURE_GSMBA and its scattered-CPUID entry
(0x80000020 EBX[8]).
- Add RDT_FLAG_GSMBA and the corresponding rdt_options entry so the
existing rdt= kernel parameter accepts "gsmba".

The GLSBE feature is documented in:

AMD64 Zen6 Platform Quality of Service (PQOS) Extensions,
Publication # 69193 Revision 1.00, Issue Date March 2026

available at https://bugzilla.kernel.org/show_bug.cgi?id=206537

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
v2: Clarify that the GLSBE control domain is aligned to NPS and that NPS
is configured via the BIOS setup utility.
---
Documentation/admin-guide/kernel-parameters.txt | 2 +-
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/resctrl/core.c | 2 ++
arch/x86/kernel/cpu/scattered.c | 1 +
4 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index f23cad453f17..03c89f90da84 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -6452,7 +6452,7 @@ Kernel parameters
rdt= [HW,X86,RDT]
Turn on/off individual RDT features. List is:
cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp,
- mba, gmba, smba, bmec, abmc, sdciae, energy[:guid],
+ mba, gmba, smba, gsmba, bmec, abmc, sdciae, energy[:guid],
perf[:guid].
E.g. to turn on cmt and turn off mba use:
rdt=cmt,!mba
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 356f7a11d47c..947935fee7c5 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -516,6 +516,7 @@
*/
#define X86_FEATURE_X2AVIC_EXT (21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */
#define X86_FEATURE_GMBA (21*32+21) /* Global Memory Bandwidth Allocation */
+#define X86_FEATURE_GSMBA (21*32+22) /* Global Slow Memory Bandwidth Enforcement */

/*
* BUG word(s)
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 22114ff84bfa..667ff3eb57f5 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -838,6 +838,7 @@ enum {
RDT_FLAG_MBA,
RDT_FLAG_GMBA,
RDT_FLAG_SMBA,
+ RDT_FLAG_GSMBA,
RDT_FLAG_BMEC,
RDT_FLAG_ABMC,
RDT_FLAG_SDCIAE,
@@ -866,6 +867,7 @@ static struct rdt_options rdt_options[] __ro_after_init = {
RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA),
RDT_OPT(RDT_FLAG_GMBA, "gmba", X86_FEATURE_GMBA),
RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA),
+ RDT_OPT(RDT_FLAG_GSMBA, "gsmba", X86_FEATURE_GSMBA),
RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC),
RDT_OPT(RDT_FLAG_ABMC, "abmc", X86_FEATURE_ABMC),
RDT_OPT(RDT_FLAG_SDCIAE, "sdciae", X86_FEATURE_SDCIAE),
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 077cf452c257..7a57453a3dcb 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -61,6 +61,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_ABMC, CPUID_EBX, 5, 0x80000020, 0 },
{ X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 },
{ X86_FEATURE_GMBA, CPUID_EBX, 7, 0x80000020, 0 },
+ { X86_FEATURE_GSMBA, CPUID_EBX, 8, 0x80000020, 0 },
{ X86_FEATURE_TSA_SQ_NO, CPUID_ECX, 1, 0x80000021, 0 },
{ X86_FEATURE_TSA_L1_NO, CPUID_ECX, 2, 0x80000021, 0 },
{ X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 },
--
2.43.0