From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A0133033D6 for ; Tue, 14 Apr 2026 17:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776188794; cv=none; b=lL8tTYxu67EnWbdRb/qgY32xyrlp5tncTaxhvoiesrElFJpZiH624g25pM3Inx6nQDTkMzTlySXegNvTLvS7eUJ17nS3ncGON7EIcPKmnHSP/OC5I1NyUFJ0Pf81G3EnL7Hc6pPM4QdIXxL+9F7kFDY9Z4NsujjwZkWaxyZBz3w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776188794; c=relaxed/simple; bh=xmt7s/twQSu4aPxzKgIdkdZzdmbSv5AWDgrjt5WYi8Q=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rlWZaKOXZkumvAWi7w2iOWD0068qvJ52Ere6ieUEQrV78WR2d6yy897731lOZp+gQxyuLQ+v5L8EOVbQpvDHeW1tzK2IBQf/O4qQYKEFvDuZ4xhKVkQsUXQtF+vHQ1dYRxWZN4Ww2neh5SLsJdOmC+s7V7aercccvs4tWQvztcI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=RiVso49o; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="RiVso49o" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1776188780; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aRLMPgmEQNtIZ1+s3R+uauqPySY8kfsW8C0JvL3DnhI=; b=RiVso49oHMRT5XG/F91j0pD7x6IqHgQbtqMpyhzFq94sPN9gPK2R0IIVei0IypZxTRX+gm V5lktbqZR6nixC7Y9yTwLsbbiY6dFKpoiDW8umfx64qbPEV8/QPr23d4zqt9ZqASRACHpw v6g7f+YNzBMV/iQr+TX1hGYRmmMzc4U= Date: Tue, 14 Apr 2026 18:46:14 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2 2/6] bus: mhi: host: Add support for non-posted TSC timesync feature To: Krishna Chaitanya Chundru , Manivannan Sadhasivam , Richard Cochran Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Vivek Pernamitta References: <20260411-tsc_timesync-v2-0-6f25f72987b3@oss.qualcomm.com> <20260411-tsc_timesync-v2-2-6f25f72987b3@oss.qualcomm.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Vadim Fedorenko In-Reply-To: <20260411-tsc_timesync-v2-2-6f25f72987b3@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 11/04/2026 09:12, Krishna Chaitanya Chundru wrote: > From: Vivek Pernamitta > > Implement non-posted time synchronization as described in section 5.1.1 > of the MHI v1.2 specification. The host disables low-power link states > to minimize latency, reads the local time, issues a MMIO read to the > device's TIME register. > > Add support for initializing this feature and export a function to be > used by the drivers which does the time synchronization. > > MHI reads the device time registers in the MMIO address space pointed to > by the capability register after disabling all low power modes and keeping > MHI in M0. Before and after MHI reads, the local time is captured > and shared for processing. [...] > + /* > + * time critical code to fetch device time, delay between these two steps > + * should be deterministic as possible. > + */ > + preempt_disable(); > + local_irq_disable(); > + > + time->t_host_pre = ktime_get_real(); > + > + /* > + * To ensure the PCIe link is in L0 when ASPM is enabled, perform series > + * of back-to-back reads. This is necessary because the link may be in a > + * low-power state (e.g., L1 or L1ss), and need to be forced it to > + * transition to L0. > + */ > + for (i = 0; i < MHI_NUM_BACK_TO_BACK_READS; i++) { > + ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg, > + TSC_TIMESYNC_TIME_LOW_OFFSET, &time->t_dev_lo); > + > + ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg, > + TSC_TIMESYNC_TIME_HIGH_OFFSET, &time->t_dev_hi); > + } > + > + time->t_host_post = ktime_get_real(); > + > + local_irq_enable(); > + preempt_enable(); PTP_SYS_OFFSET_EXTENDED receives the amount of samples to read from user space, you can use it instead of MHI_NUM_BACK_TO_BACK_READS, and in this case it's better to grab host-pre and host-post time for a single register read. Also, PTP_SYS_OFFSET_EXTENDED was improved and currently supports multiple clockids as system time, it's good to account for it.