From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5014CC77B6E for ; Wed, 12 Apr 2023 13:13:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231159AbjDLNNH (ORCPT ); Wed, 12 Apr 2023 09:13:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230167AbjDLNMn (ORCPT ); Wed, 12 Apr 2023 09:12:43 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAE2B83FC for ; Wed, 12 Apr 2023 06:12:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681305153; x=1712841153; h=message-id:date:mime-version:cc:subject:to:references: from:in-reply-to:content-transfer-encoding; bh=pHDdNub1XE313y0o+udCKvVcUwWqzEfrQeWMSLbvAXY=; b=ZL9lgEd8+bItdMUwfIhu27E741I3LSug9fuv3Xzu8c6wsEU7s/q7Mxsz PSJUvaLYNxeYNlpv9r3XTKtXvf3mwcPiVSAYmFLUQf5ilx0HOxVSZSTez tjD0wjtpO4h+HrAkTco2gfVqztHz5VL4VqHLzdcL+elmV/JED6mmGVQPb UMv5YBhC0WQgzXYQC1w5R1u/AI59+zkUVcBsVhr88J0wYTzcBY8WELXl9 X04w8QKfprcWwUWvFwlyvC9ipXk5Fo395dkN/O0tun8Dy41c/r2gF73vE MXb4bY7xBUuTfj3qrTot1ZiQk69/hbHK32EUQkrEw28RrAfwrnAC5AFyl A==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="332586538" X-IronPort-AV: E=Sophos;i="5.98,339,1673942400"; d="scan'208";a="332586538" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 06:10:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="721563470" X-IronPort-AV: E=Sophos;i="5.98,339,1673942400"; d="scan'208";a="721563470" Received: from blu2-mobl.ccr.corp.intel.com (HELO [10.254.215.58]) ([10.254.215.58]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 06:10:32 -0700 Message-ID: Date: Wed, 12 Apr 2023 21:10:30 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Cc: baolu.lu@linux.intel.com, Vinod Koul , Tina Zhang , Jacob Pan , Christophe JAILLET , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 11/17] iommu/vt-d: Fix operand size in bitwise operation To: David Laight , Joerg Roedel References: <20230411064815.31456-1-baolu.lu@linux.intel.com> <20230411064815.31456-12-baolu.lu@linux.intel.com> <6d9ed10d-12ee-792f-fc34-60a8e432c5d2@linux.intel.com> Content-Language: en-US From: Baolu Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023/4/12 15:11, David Laight wrote: > From: Baolu Lu >> Sent: 12 April 2023 02:32 >> >> On 4/12/23 5:22 AM, David Laight wrote: >>>> Sent: 11 April 2023 07:48 >>>> >>>> From: Tina Zhang >>>> >>>> The patch fixes the klocwork issues that operands in a bitwise operation >>>> have different size at line 1692 of dmar.c, line 1898 and line 1907 of >>>> iommu.c. >>> Why is this any kind of thing that needs fixing? >> >> This description is a bit misleading. Actually I queued it as a cleanup >> patch. > > Hopefully without 'fix' anywhere in the description. > Otherwise the scripts will pick it for a back-port. Fair enough.I will refine the commit message like below: iommu/vt-d: Make size of operands same in bitwise operations The addresses the following issue reported by klocwork tool: - operands of different size in bitwise operations Suggested-by: Yongwei Ma Signed-off-by: Tina Zhang > >>> - val |= (1 << 11) | 1; >>> + val |= BIT_ULL(11) | BIT_ULL(0); > > More problematic it what is bit 11 anyway? There is already a comment at the top of the code explaining the meaning of these bits. Because this is not a newly added code, it is not displayed in this patch. /* * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability * is present. */ if (ecap_smts(iommu->ecap)) val |= BIT_ULL(11) | BIT_ULL(0); Best regards, baolu