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X-CSE-ConnectionGUID: d3JEz/PLSg2a5FiCkG0djg== X-CSE-MsgGUID: sg0xEQraQfizLwRsCO0YhQ== X-IronPort-AV: E=McAfee;i="6700,10204,11190"; a="42133120" X-IronPort-AV: E=Sophos;i="6.10,215,1719903600"; d="scan'208";a="42133120" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2024 17:49:52 -0700 X-CSE-ConnectionGUID: pqNkPw70ToWZ0/N04HPcOA== X-CSE-MsgGUID: T0B/ezBGTA2+ACdPC2PSFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,215,1719903600"; d="scan'208";a="71820323" Received: from xpardee-mobl.amr.corp.intel.com (HELO [10.125.67.115]) ([10.125.67.115]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2024 17:49:52 -0700 Message-ID: Date: Mon, 9 Sep 2024 17:49:51 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 11/11] platform/x86:intel/pmc: Get LPM information for Lunar Lake To: =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= Cc: irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, Hans de Goede , platform-driver-x86@vger.kernel.org, LKML , linux-pm@vger.kernel.org References: <20240828222932.1279508-1-xi.pardee@linux.intel.com> <20240828222932.1279508-12-xi.pardee@linux.intel.com> Content-Language: en-US From: Xi Pardee In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 8/29/2024 5:13 AM, Ilpo Järvinen wrote: > On Wed, 28 Aug 2024, Xi Pardee wrote: > >> Add support to find and read the requirements from the telemetry >> entries for Lunar Lake platforms. >> >> Signed-off-by: Xi Pardee >> --- >> drivers/platform/x86/intel/pmc/lnl.c | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c >> index 109b08d43fc8..f5fee9e105e2 100644 >> --- a/drivers/platform/x86/intel/pmc/lnl.c >> +++ b/drivers/platform/x86/intel/pmc/lnl.c >> @@ -13,8 +13,13 @@ >> >> #include "core.h" >> >> +#define SOCM_LPM_REQ_GUID 0x15099748 >> + >> +static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; >> + >> static struct pmc_info lnl_pmc_info_list[] = { >> { >> + .guid = SOCM_LPM_REQ_GUID, >> .devid = PMC_DEVID_LNL_SOCM, >> .map = &lnl_socm_reg_map, >> }, >> @@ -536,6 +541,7 @@ const struct pmc_reg_map lnl_socm_reg_map = { >> .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, >> .s0ix_blocker_maps = lnl_blk_maps, >> .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, >> + .lpm_reg_index = LNL_LPM_REG_INDEX, >> }; >> >> #define LNL_NPU_PCI_DEV 0x643e >> @@ -561,6 +567,8 @@ static int lnl_resume(struct pmc_dev *pmcdev) >> >> int lnl_core_init(struct pmc_dev *pmcdev) >> { >> + bool ssram_init = true; >> + int func = 2; >> int ret; >> struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; >> >> @@ -578,6 +586,7 @@ int lnl_core_init(struct pmc_dev *pmcdev) >> >> /* If regbase not assigned, set map and discover using legacy method */ >> if (ret) { >> + ssram_init = false; >> pmc->map = &lnl_socm_reg_map; >> ret = get_primary_reg_base(pmc); >> if (ret) >> @@ -586,5 +595,11 @@ int lnl_core_init(struct pmc_dev *pmcdev) >> >> pmc_core_get_low_power_modes(pmcdev); >> >> + if (ssram_init) { >> + ret = pmc_core_ssram_get_lpm_reqs(pmcdev, func); >> + if (ret) >> + return ret; > There's quite much duplication related to this legacy/ssram init in > the per arch core init functions. And some inconsistencies too which > seem incidental such as mtl.c using return directly here. I will try to extract the duplicate code to a common function and remove the inconsistencies between different architecture in next version. Xi