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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Mike Leach <mike.leach@linaro.org>,
	James Clark <james.clark@arm.com>, Leo Yan <leo.yan@linaro.org>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-doc@vger.kernel.org, coresight@lists.linaro.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V5 - RESEND 3/3] Documentation: coresight: Add cc_threshold tunable
Date: Wed, 20 Sep 2023 10:25:20 +0100	[thread overview]
Message-ID: <cd4e78fb-7385-6db4-b558-4599b0cdcbff@arm.com> (raw)
In-Reply-To: <20230915093649.435163-4-anshuman.khandual@arm.com>

On 15/09/2023 10:36, Anshuman Khandual wrote:
> This updates config option to include 'cc_threshold' tunable value.
> 
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: James Clark <james.clark@arm.com>
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Reviewed by: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>   Documentation/trace/coresight/coresight.rst | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst
> index 4a71ea6cb390..ce55adb80b82 100644
> --- a/Documentation/trace/coresight/coresight.rst
> +++ b/Documentation/trace/coresight/coresight.rst
> @@ -624,6 +624,10 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/
>      * - timestamp
>        - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP
>          <coresight-timestamp>`
> +   * - cc_threshold
> +     - Cycle count threshold value. If nothing is provided here or the provided value is 0, then the
> +       default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold
> +       value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead.
>   
>   How to use the STM module
>   -------------------------

The patch as such looks good to me. If possible, could you fold this 
into the previous patch ?

Suzuki

  reply	other threads:[~2023-09-20  9:26 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-15  9:36 [PATCH V5 - RESEND 0/3] coresight: etm: Make cycle count threshold user configurable Anshuman Khandual
2023-09-15  9:36 ` [PATCH V5 - RESEND 1/3] coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus Anshuman Khandual
2023-09-19 11:06   ` Mike Leach
2023-09-19 11:26   ` Suzuki K Poulose
2023-09-20  6:40     ` Anshuman Khandual
2023-09-20  8:49       ` Mike Leach
2023-09-20  9:11       ` Suzuki K Poulose
2023-09-15  9:36 ` [PATCH V5 - RESEND 2/3] coresight: etm: Make cycle count threshold user configurable Anshuman Khandual
2023-09-19 11:07   ` Mike Leach
2023-09-20  9:22   ` Suzuki K Poulose
2023-09-20 10:44     ` Anshuman Khandual
2023-09-15  9:36 ` [PATCH V5 - RESEND 3/3] Documentation: coresight: Add cc_threshold tunable Anshuman Khandual
2023-09-20  9:25   ` Suzuki K Poulose [this message]
2023-09-20 10:41     ` Anshuman Khandual

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