Re: [PATCH 2/2] PCI: Resources outside their window must set IORESOURCE_UNSET

Ilpo Järvinen
2025-10-01T13:06:14Z

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On Wed, 1 Oct 2025, Geert Uytterhoeven wrote:
> On Tue, 30 Sept 2025 at 18:32, Ilpo Järvinen
> <ilpo.jarvinen@linux.intel.com> wrote:
> > On Tue, 30 Sep 2025, Geert Uytterhoeven wrote:
> > > On Fri, 26 Sept 2025 at 04:40, Ilpo Järvinen
> > > <ilpo.jarvinen@linux.intel.com> wrote:
> > > > PNP resources are checked for conflicts with the other resource in the
> > > > system by quirk_system_pci_resources() that walks through all PCI
> > > > resources. quirk_system_pci_resources() correctly filters out resource
> > > > with IORESOURCE_UNSET.
> > > >
> > > > Resources that do not reside within their bridge window, however, are
> > > > not properly initialized with IORESOURCE_UNSET resulting in bogus
> > > > conflicts detected in quirk_system_pci_resources():
> > > >
> > > > pci 0000:00:02.0: VF BAR 2 [mem 0x00000000-0x1fffffff 64bit pref]
> > > > pci 0000:00:02.0: VF BAR 2 [mem 0x00000000-0xdfffffff 64bit pref]: contains BAR 2 for 7 VFs
> > > > ...
> > > > pci 0000:03:00.0: VF BAR 2 [mem 0x00000000-0x1ffffffff 64bit pref]
> > > > pci 0000:03:00.0: VF BAR 2 [mem 0x00000000-0x3dffffffff 64bit pref]: contains BAR 2 for 31 VFs
> > > > ...
> > > > pnp 00:04: disabling [mem 0xfc000000-0xfc00ffff] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xc0000000-0xcfffffff] because it overlaps 0000:00:02.0 BAR 9 [mem 0x00000000-0xdfffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xfedc0000-0xfedc7fff] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xfeda0000-0xfeda0fff] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xfeda1000-0xfeda1fff] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xc0000000-0xcfffffff disabled] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xfed20000-0xfed7ffff] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xfed90000-0xfed93fff] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xfed45000-0xfed8ffff] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > > pnp 00:05: disabling [mem 0xfee00000-0xfeefffff] because it overlaps 0000:03:00.0 BAR 9 [mem 0x00000000-0x3dffffffff 64bit pref]
> > > >
> > > > Mark resources that are not contained within their bridge window with
> > > > IORESOURCE_UNSET in __pci_read_base() which resolves the false
> > > > positives for the overlap check in quirk_system_pci_resources().
> > > >
> > > > Fixes: f7834c092c42 ("PNP: Don't check for overlaps with unassigned PCI BARs")
> > > > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> > >
> > > Thanks for your patch, which is now commit 06b77d5647a4d6a7 ("PCI:
> > > Mark resources IORESOURCE_UNSET when outside bridge windows") in
> > > linux-next/master next-20250929 pci/next
>
> > > This replaces the actual resources by their sizes in the boot log on
> > > e.g. on R-Car M2-W:
> > >
> > > pci-rcar-gen2 ee090000.pci: host bridge /soc/pci@ee090000 ranges:
> > > pci-rcar-gen2 ee090000.pci: MEM 0x00ee080000..0x00ee08ffff -> 0x00ee080000
> > > pci-rcar-gen2 ee090000.pci: PCI: revision 11
> > > pci-rcar-gen2 ee090000.pci: PCI host bridge to bus 0000:00
> > > pci_bus 0000:00: root bus resource [bus 00]
> > > pci_bus 0000:00: root bus resource [mem 0xee080000-0xee08ffff]
> > > pci 0000:00:00.0: [1033:0000] type 00 class 0x060000 conventional PCI endpoint
> > > -pci 0000:00:00.0: BAR 0 [mem 0xee090800-0xee090bff]
> > > -pci 0000:00:00.0: BAR 1 [mem 0x40000000-0x7fffffff pref]
> >
> > What is going to be the parent of these resources? They don't seem to fall
> > under the root bus resource above in which case the output change is
> > intentional so they don't appear as if address range would be "okay".
>
> >From /proc/iomem:
>
> ee080000-ee08ffff : pci@ee090000
> ee080000-ee080fff : 0000:00:01.0
> ee080000-ee080fff : ohci_hcd
> ee081000-ee0810ff : 0000:00:02.0
> ee081000-ee0810ff : ehci_hcd
> ee090000-ee090bff : ee090000.pci pci@ee090000

Okay, so this seem to appear in the resource tree but not among the root
bus resources.

> ee0c0000-ee0cffff : pci@ee0d0000
> ee0c0000-ee0c0fff : 0001:01:01.0
> ee0c0000-ee0c0fff : ohci_hcd
> ee0c1000-ee0c10ff : 0001:01:02.0
> ee0c1000-ee0c10ff : ehci_hcd
>
> > When IORESOURCE_UNSET is set in a resource, %pR does not print the start
> > and end addresses.
>
> Yeah, that's how I found this commit, without bisecting ;-)
>
> > > +pci 0000:00:00.0: BAR 0 [mem size 0x00000400]
> > > +pci 0000:00:00.0: BAR 1 [mem size 0x40000000 pref]
> > > pci 0000:00:01.0: [1033:0035] type 00 class 0x0c0310 conventional PCI endpoint
> > > -pci 0000:00:01.0: BAR 0 [mem 0x00000000-0x00000fff]
> > > +pci 0000:00:01.0: BAR 0 [mem size 0x00001000]
> >
> > For this resource, it's very much intentional. It's a zero-based BAR which
> > was left without IORESOURCE_UNSET prior to my patch leading to others part
> > of the kernel to think that resource range valid and in use (in your
> > case it's so small it wouldn't collide with anything but it wasn't
> > properly set up resource, nonetheless).
> >
> > > pci 0000:00:01.0: supports D1 D2
> > > pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot
> > > pci 0000:00:02.0: [1033:00e0] type 00 class 0x0c0320 conventional PCI endpoint
> > > -pci 0000:00:02.0: BAR 0 [mem 0x00000000-0x000000ff]
> > > +pci 0000:00:02.0: BAR 0 [mem size 0x00000100]
> >
> > And this as well is very much intentional.
> >
> > > pci 0000:00:02.0: supports D1 D2
> > > pci 0000:00:02.0: PME# supported from D0 D1 D2 D3hot
> > > PCI: bus0: Fast back to back transfers disabled
> > > pci 0000:00:01.0: BAR 0 [mem 0xee080000-0xee080fff]: assigned
> > > pci 0000:00:02.0: BAR 0 [mem 0xee081000-0xee0810ff]: assigned
> > > pci_bus 0000:00: resource 4 [mem 0xee080000-0xee08ffff]
> > >
> > > Is that intentional?
> >
> > There's also that pci_dbg() in the patch which would show the original
> > addresses (print the resource before setting IORESOURCE_UNSET) but to see
> > it one would need to enable it with dyndbg=... Bjorn was thinking of
> > making that pci_info() though so it would appear always.
> >
> > Was this the entire PCI related diff? I don't see those 0000:00:00.0 BARs
> > getting assigned anywhere.
>
> The above log is almost complete (lacked enabling the device afterwards).
>
> AFAIU, the BARs come from the reg and ranges properties in the
> PCI controller nodes;
> https://elixir.bootlin.com/linux/v6.17/source/arch/arm/boot/dts/renesas/r8a7791.dtsi#L1562

Thanks, although I had already found this line by grep. I was just
expecting the address appear among root bus resources too.

Curiously enough, pci_register_host_bridge() seems to try to add some
resource from that list into bus and it's what prints those "root bus
resource" lines and ee090000 is not among the printed lines despite
appearing in /proc/iomem. As is, the resource tree and PCI bus view on the
resources seems to be in disagreement and I'm not sure what to make of it.

But before considering going into that direction or figuring out why this
ee090000 resource does not appear among root bus resources, could you
check if the attached patch changes behavior for the resource which are
non-zero based?

--
i.

> The full related log for this device, for both instances, with the pci_dbg()
> changes to pci_info():
>
> pci-rcar-gen2 ee090000.pci: host bridge /soc/pci@ee090000 ranges:
> pci-rcar-gen2 ee090000.pci: MEM 0x00ee080000..0x00ee08ffff
> -> 0x00ee080000
> pci-rcar-gen2 ee090000.pci: PCI: revision 11
> pci-rcar-gen2 ee090000.pci: PCI host bridge to bus 0000:00
> pci_bus 0000:00: root bus resource [bus 00]
> pci_bus 0000:00: root bus resource [mem 0xee080000-0xee08ffff]
> pci 0000:00:00.0: [1033:0000] type 00 class 0x060000 conventional
> PCI endpoint
> -pci 0000:00:00.0: BAR 0 [mem 0xee090800-0xee090bff]
> -pci 0000:00:00.0: BAR 1 [mem 0x40000000-0x7fffffff pref]
> +pci 0000:00:00.0: BAR 0 [mem 0xee090800-0xee090bff]: no initial
> claim (no window)
> +pci 0000:00:00.0: BAR 0 [mem size 0x00000400]
> +pci 0000:00:00.0: BAR 1 [mem 0x40000000-0x7fffffff pref]: no
> initial claim (no window)
> +pci 0000:00:00.0: BAR 1 [mem size 0x40000000 pref]
> pci 0000:00:01.0: [1033:0035] type 00 class 0x0c0310 conventional
> PCI endpoint
> -pci 0000:00:01.0: BAR 0 [mem 0x00000000-0x00000fff]
> +pci 0000:00:01.0: BAR 0 [mem 0x00000000-0x00000fff]: no initial
> claim (no window)
> +pci 0000:00:01.0: BAR 0 [mem size 0x00001000]
> pci 0000:00:01.0: supports D1 D2
> pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot
> pci 0000:00:02.0: [1033:00e0] type 00 class 0x0c0320 conventional
> PCI endpoint
> -pci 0000:00:02.0: BAR 0 [mem 0x00000000-0x000000ff]
> +pci 0000:00:02.0: BAR 0 [mem 0x00000000-0x000000ff]: no initial
> claim (no window)
> +pci 0000:00:02.0: BAR 0 [mem size 0x00000100]
> pci 0000:00:02.0: supports D1 D2
> pci 0000:00:02.0: PME# supported from D0 D1 D2 D3hot
> PCI: bus0: Fast back to back transfers disabled
> pci 0000:00:01.0: BAR 0 [mem 0xee080000-0xee080fff]: assigned
> pci 0000:00:02.0: BAR 0 [mem 0xee081000-0xee0810ff]: assigned
> pci_bus 0000:00: resource 4 [mem 0xee080000-0xee08ffff]
> pci 0000:00:01.0: enabling device (0140 -> 0142)
> pci 0000:00:02.0: enabling device (0140 -> 0142)
> pci-rcar-gen2 ee0d0000.pci: host bridge /soc/pci@ee0d0000 ranges:
> pci-rcar-gen2 ee0d0000.pci: MEM 0x00ee0c0000..0x00ee0cffff
> -> 0x00ee0c0000
> pci-rcar-gen2 ee0d0000.pci: PCI: revision 11
> pci-rcar-gen2 ee0d0000.pci: PCI host bridge to bus 0001:01
> pci_bus 0001:01: root bus resource [bus 01]
> pci_bus 0001:01: root bus resource [mem 0xee0c0000-0xee0cffff]
> pci 0001:01:00.0: [1033:0000] type 00 class 0x060000 conventional
> PCI endpoint
> -pci 0001:01:00.0: BAR 0 [mem 0xee0d0800-0xee0d0bff]
> -pci 0001:01:00.0: BAR 1 [mem 0x40000000-0x7fffffff pref]
> +pci 0001:01:00.0: BAR 0 [mem 0xee0d0800-0xee0d0bff]: no initial
> claim (no window)
> +pci 0001:01:00.0: BAR 0 [mem size 0x00000400]
> +pci 0001:01:00.0: BAR 1 [mem 0x40000000-0x7fffffff pref]: no
> initial claim (no window)
> +pci 0001:01:00.0: BAR 1 [mem size 0x40000000 pref]
> pci 0001:01:01.0: [1033:0035] type 00 class 0x0c0310 conventional
> PCI endpoint
> -pci 0001:01:01.0: BAR 0 [mem 0x00000000-0x00000fff]
> +pci 0001:01:01.0: BAR 0 [mem 0x00000000-0x00000fff]: no initial
> claim (no window)
> +pci 0001:01:01.0: BAR 0 [mem size 0x00001000]
> pci 0001:01:01.0: supports D1 D2
> pci 0001:01:01.0: PME# supported from D0 D1 D2 D3hot
> pci 0001:01:02.0: [1033:00e0] type 00 class 0x0c0320 conventional
> PCI endpoint
> -pci 0001:01:02.0: BAR 0 [mem 0x00000000-0x000000ff]
> +pci 0001:01:02.0: BAR 0 [mem 0x00000000-0x000000ff]: no initial
> claim (no window)
> +pci 0001:01:02.0: BAR 0 [mem size 0x00000100]
> pci 0001:01:02.0: supports D1 D2
> pci 0001:01:02.0: PME# supported from D0 D1 D2 D3hot
> PCI: bus1: Fast back to back transfers disabled
> pci 0001:01:01.0: BAR 0 [mem 0xee0c0000-0xee0c0fff]: assigned
> pci 0001:01:02.0: BAR 0 [mem 0xee0c1000-0xee0c10ff]: assigned
> pci_bus 0001:01: resource 4 [mem 0xee0c0000-0xee0cffff]
> pci 0001:01:01.0: enabling device (0140 -> 0142)
> pci 0001:01:02.0: enabling device (0140 -> 0142)
>
> > You didn't report any issues beyond textual changes in the log, I suppose
> > there were none beyond the log differences?
>
> Sorry, I should have done a little bit more testing. This is the funny
> on-chip Renesas R-Car Gen2 PCI host controller with integrated OHCI/EHCI
> PCI devices. I don't have any USB devices connected, but "lspci -v"
> output is the same before/after, and the OHCI/EHCI drivers probe fine.
>
> BTW, I am seeing similar changes on rts7751r2d (qemu SuperH target r2d):
>
> PCI host bridge to bus 0000:00
> pci_bus 0000:00: root bus resource [io 0x1000-0x3fffff]
> pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfdffffff]
> pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
> pci 0000:00:00.0: [1054:350e] type 00 class 0x060000 conventional
> PCI endpoint
> pci 0000:00:00.0: [Firmware Bug]: BAR 0: invalid; can't size
> pci 0000:00:00.0: [Firmware Bug]: BAR 1: invalid; can't size
> pci 0000:00:00.0: [Firmware Bug]: BAR 2: invalid; can't size
> pci 0000:00:02.0: [10ec:8139] type 00 class 0x020000 conventional
> PCI endpoint
> -pci 0000:00:02.0: BAR 0 [io 0x0000-0x00ff]
> -pci 0000:00:02.0: BAR 1 [mem 0x00000000-0x000000ff]
> -pci 0000:00:02.0: ROM [mem 0x00000000-0x0007ffff pref]
> +pci 0000:00:02.0: BAR 0 [io 0x0000-0x00ff]: no initial claim (no window)
> +pci 0000:00:02.0: BAR 0 [io size 0x0100]
> +pci 0000:00:02.0: BAR 1 [mem 0x00000000-0x000000ff]: no initial
> claim (no window)
> +pci 0000:00:02.0: BAR 1 [mem size 0x00000100]
> +pci 0000:00:02.0: ROM [mem 0x00000000-0x0007ffff pref]: no
> initial claim (no window)
> +pci 0000:00:02.0: ROM [mem size 0x00080000 pref]
> pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 00
> pci 0000:00:02.0: ROM [mem 0xfd000000-0xfd07ffff pref]: assigned
> pci 0000:00:02.0: BAR 0 [io 0x1000-0x10ff]: assigned
> pci 0000:00:02.0: BAR 1 [mem 0xfd080000-0xfd0800ff]: assigned
>
> All of these look legitimate to me, as they all start at zero.
>
> Thanks!
>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>

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From: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH] PCI: Check also host bridge windows in pbus_select_window_for_res_addr()

Check also host bridge windows in pbus_select_window_for_res_addr() as
they don't seem to appear in appear as root bus resources.

Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

---
drivers/pci/probe.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 097389f25853..66f0763113cb 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -206,10 +206,12 @@ static void __pci_size_rom(struct pci_dev *dev, unsigned int pos, u32 *sizes)
}

static struct resource *pbus_select_window_for_res_addr(
- const struct pci_bus *bus,
+ struct pci_bus *bus,
const struct resource *res)
{
unsigned long type = res->flags & IORESOURCE_TYPE_BITS;
+ struct pci_host_bridge *host_bridge;
+ struct resource_entry *window;
struct resource *r;

pci_bus_for_each_resource(bus, r) {
@@ -222,6 +224,19 @@ static struct resource *pbus_select_window_for_res_addr(
if (resource_contains(r, res))
return r;
}
+
+ if (!pci_is_root_bus(bus))
+ return NULL;
+
+ host_bridge = pci_find_host_bridge(bus);
+ resource_list_for_each_entry(window, &host_bridge->windows) {
+ if ((window->res->flags & IORESOURCE_TYPE_BITS) != type)
+ continue;
+
+ if (resource_contains(window->res, res))
+ return r;
+ }
+
return NULL;
}

--
tg: (7970e5d038d5..) fix/check-host-bridge-windows (depends on: fix/iov-resource-init)