From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDE3FC433EF for ; Thu, 11 Nov 2021 16:58:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BBF8E61354 for ; Thu, 11 Nov 2021 16:58:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234222AbhKKRB0 (ORCPT ); Thu, 11 Nov 2021 12:01:26 -0500 Received: from so254-9.mailgun.net ([198.61.254.9]:28379 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229539AbhKKRBY (ORCPT ); Thu, 11 Nov 2021 12:01:24 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1636649915; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: From: References: Cc: To: Subject: MIME-Version: Date: Message-ID: Sender; bh=Fm+8CbAWSdAcP/8qZCXokIpOIPGShPhL8uLwQhrTmh8=; b=vAPsyi4uLYiv7gzV8fxNZ1h8nXG5gLw2OdlMrSBon+PRA9Dp+hO5bznN5bgMzOWLIS8AAIHq 5hDhiv699oM2dboZ4oaE5Dyhlskqd6amJ4T5WS6a6QdZeJ0INPKhEIn8EJLqqwssj4zJfIx5 LgAG5YX0LgYUS+eMCb2efdIRr0Y= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-east-1.postgun.com with SMTP id 618d4bb01b212dbdbde1f31d (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 11 Nov 2021 16:58:24 GMT Sender: akhilpo=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9C41AC4360D; Thu, 11 Nov 2021 16:58:23 +0000 (UTC) Received: from [192.168.1.16] (unknown [117.210.184.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 158DFC4338F; Thu, 11 Nov 2021 16:58:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 158DFC4338F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org Message-ID: Date: Thu, 11 Nov 2021 22:28:16 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.1.1 Subject: Re: [PATCH 4/5] drm/msm: Handle fence rollover Content-Language: en-US To: Rob Clark , dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Jordan Crouse , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , open list References: <20211109181117.591148-1-robdclark@gmail.com> <20211109181117.591148-5-robdclark@gmail.com> From: Akhil P Oommen In-Reply-To: <20211109181117.591148-5-robdclark@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/9/2021 11:41 PM, Rob Clark wrote: > From: Rob Clark > > Add some helpers for fence comparision, which handle rollover properly, > and stop open coding fence seqno comparisions. > > Signed-off-by: Rob Clark > --- > drivers/gpu/drm/msm/msm_fence.h | 12 ++++++++++++ > drivers/gpu/drm/msm/msm_gpu.c | 6 +++--- > drivers/gpu/drm/msm/msm_gpu.h | 2 +- > 3 files changed, 16 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/msm_fence.h b/drivers/gpu/drm/msm/msm_fence.h > index 4783db528bcc..17ee3822b423 100644 > --- a/drivers/gpu/drm/msm/msm_fence.h > +++ b/drivers/gpu/drm/msm/msm_fence.h > @@ -60,4 +60,16 @@ void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence); > > struct dma_fence * msm_fence_alloc(struct msm_fence_context *fctx); > > +static inline bool > +fence_before(uint32_t a, uint32_t b) > +{ > + return (int32_t)(a - b) < 0; This is good enough when a and b have close values. And that is a good assumption for KMD generated seqno. Reviewed-by: Akhil P Oommen -Akhil. > +} > + > +static inline bool > +fence_after(uint32_t a, uint32_t b) > +{ > + return (int32_t)(a - b) > 0; > +} > + > #endif > diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c > index 13de1241d595..0f78c2615272 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.c > +++ b/drivers/gpu/drm/msm/msm_gpu.c > @@ -172,7 +172,7 @@ static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > > spin_lock_irqsave(&ring->submit_lock, flags); > list_for_each_entry(submit, &ring->submits, node) { > - if (submit->seqno > fence) > + if (fence_after(submit->seqno, fence)) > break; > > msm_update_fence(submit->ring->fctx, > @@ -509,7 +509,7 @@ static void hangcheck_handler(struct timer_list *t) > if (fence != ring->hangcheck_fence) { > /* some progress has been made.. ya! */ > ring->hangcheck_fence = fence; > - } else if (fence < ring->seqno) { > + } else if (fence_before(fence, ring->seqno)) { > /* no progress and not done.. hung! */ > ring->hangcheck_fence = fence; > DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", > @@ -523,7 +523,7 @@ static void hangcheck_handler(struct timer_list *t) > } > > /* if still more pending work, reset the hangcheck timer: */ > - if (ring->seqno > ring->hangcheck_fence) > + if (fence_after(ring->seqno, ring->hangcheck_fence)) > hangcheck_timer_reset(gpu); > > /* workaround for missing irq: */ > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index 0dcc31c27ac3..bd4e0024033e 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -258,7 +258,7 @@ static inline bool msm_gpu_active(struct msm_gpu *gpu) > for (i = 0; i < gpu->nr_rings; i++) { > struct msm_ringbuffer *ring = gpu->rb[i]; > > - if (ring->seqno > ring->memptrs->fence) > + if (fence_after(ring->seqno, ring->memptrs->fence)) > return true; > } > >