From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A6833B6DF for ; Wed, 15 Jul 2026 16:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784132474; cv=none; b=oZ7KR8NPNe246YPcZve6WFPqZE6/1W0vK1VfFGn+h30QYXJXLPSfpZH06Z06hMuUg0ma9dnLi0qnI88WVPNMmbEPK8cgFmDJ4eOmrfh6fEEiWxT/UcyvrwB/4ZWpYv9lIhG3dSxHCyFsbXcllpZ7y6BnK7KTSKHY3ZENxwRIk6M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784132474; c=relaxed/simple; bh=iELZkuZ/w3a0GLMnils6RDk8dnAkrtRWq+RqeKXa6qg=; h=Date:From:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=Wuf0aUyA+8MD6W3lOQnqMipZrWLegEG2OtSuSZ9AHUzoDPyk5TyNRb+Fiv1a0cvOjUIAtnSJU0GujwtxmUlgR00DrTdQ3EnXHXZ6omO5qZwvsygD7RCf0rg2Dk8p90OjO3HwzwJe0Rb1Jd3OLNJ/cUanLKsZQV4QtgT9ZZChL8I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YbTPT4Wu; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YbTPT4Wu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D65E1F000E9; Wed, 15 Jul 2026 16:21:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784132473; bh=D9crtScMd6wKRa8Dd1rnpK7lHl213SFq9ZDSAcbKOZM=; h=Date:From:To:cc:Subject:In-Reply-To:References; b=YbTPT4WuylWKGZpQ1j/R8LwwfLP14NiZfBhNl1eYzLYbiPQwwKULdKfGNbeHRDSWB tVPNpVIZ2gHYyON632UDTKVWp7DkGfIyHgRgCI0WrpKCm35zq/w/SS1mtQa9Vxsgyj OFQEnorhcbHZvYCk9qQW2x/ahjIR1pWP9ELA0xaniWTe+yl3LHcntNmbrk5mY3m+SB wrTc0wP6KvOnjTdwivwZqsFiWWqOeNYM6qTRrPDqW+oW97hmPbh7FJsKldDnAo704u HSVSSnNWKmVigJYhgABIC5smTh56C5YYOHs9ChQ/g9wQFBmtlhYDmWztYoAwlxTXZu QMYrtGxXX1Hwg== Date: Wed, 15 Jul 2026 10:21:09 -0600 (MDT) From: Paul Walmsley To: Himanshu Chauhan cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, shuah@kernel.org Subject: Re: [PATCH v4 0/2] riscv: Introduce support for hardware break/watchpoints In-Reply-To: <20260518065920.872131-1-himanshu.chauhan@oss.qualcomm.com> Message-ID: References: <20260518065920.872131-1-himanshu.chauhan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Hi, On Mon, 18 May 2026, Himanshu Chauhan wrote: > This patchset adds support of hardware breakpoints and watchpoints in RISC-V > architecture. The framework is built on top of perf subsystem and SBI debug > trigger extension. > > Currently following features are not supported and are in works: > - Ptrace support > - Single stepping > - Virtualization of debug triggers Thanks for the patches. Looks like it breaks rv32 builds. Can you check that and update? thanks, - Paul