Re: [PATCH 2/7] x86/mce: Enumeration updates for Intel bitfix filter reset

["Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>]

On Tue, 25 Aug 2026, Tony Luck wrote:

> IA32_CORE_CAPABILITIES enumerates the bitfix filter reset feature.
> 
> Also add definitions for the threshold status field in the machine
> check status registers.
> 
> Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
>  arch/x86/include/asm/mce.h       | 6 ++++++
>  arch/x86/include/asm/msr-index.h | 2 ++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> index e575b702063d..0d5bcb6f1750 100644
> --- a/arch/x86/include/asm/mce.h
> +++ b/arch/x86/include/asm/mce.h
> @@ -13,6 +13,7 @@
>  #define MCG_CTL_P		BIT_ULL(8)   /* MCG_CTL register available */
>  #define MCG_EXT_P		BIT_ULL(9)   /* Extended registers available */
>  #define MCG_CMCI_P		BIT_ULL(10)  /* CMCI supported */
> +#define MCG_TES_P		BIT_ULL(11)  /* Threshold-based error status supported */
>  #define MCG_SEAM_NR		BIT_ULL(12)  /* MCG_STATUS_SEAM_NR supported */
>  #define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
>  #define MCG_EXT_CNT_SHIFT	16
> @@ -41,6 +42,11 @@
>  #define MCI_STATUS_PCC		BIT_ULL(57)  /* processor context corrupt */
>  #define MCI_STATUS_S		BIT_ULL(56)  /* Signaled machine check */
>  #define MCI_STATUS_AR		BIT_ULL(55)  /* Action required */
> +#define MCI_STATUS_TES_SHIFT	53           /* Threshold-based error status */
> +#define MCI_STATUS_TES_MASK	GENMASK_ULL(54, 53)
> +#define MCI_STATUS_TES(s)	(((s) & MCI_STATUS_TES_MASK) >> MCI_STATUS_TES_SHIFT)

This opencodes FIELD_GET(), and you don't need usually need _SHIFT define 
at all when you use FIELD_GET().

> +#define  MCI_STATUS_TES_GREEN	1	     /* Threshold-based errors below threshold */
> +#define  MCI_STATUS_TES_YELLOW	2	     /* Threshold-based errors above threshold */
>  #define MCI_STATUS_CEC_SHIFT	38           /* Corrected Error Count */
>  #define MCI_STATUS_CEC_MASK	GENMASK_ULL(52,38)
>  #define MCI_STATUS_CEC(c)	(((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 18c4be75e927..13d3efc87b14 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -114,6 +114,8 @@
>  #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS	  BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
>  #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT  5
>  #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT	  BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
> +#define MSR_IA32_CORE_CAPS_BFF_RESET_DETECT_BIT   9
> +#define MSR_IA32_CORE_CAPS_BFF_RESET_DETECT	  BIT(MSR_IA32_CORE_CAPS_BFF_RESET_DETECT_BIT)
>  
>  #define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2
>  #define NHM_C3_AUTO_DEMOTE		(1UL << 25)
> 

-- 
 i.